robert_o wrote: ↑Wed Nov 17, 2021 7:58 am
I could try.
OK.
robert_o wrote: ↑Wed Nov 17, 2021 7:58 am
With the Interrupt another problem arises.
I need the Interrupt masked THE MOMENT the CPU is halted, not before. Is that possible?
It would be helpful if you could share a few more details of the problem here, rather than just stating the solution you think you need.
Are you trying to have IRQ disconnect automatically when single-stepping, and have it reconnect automatically when free running (after the continue command)
Single stepping a system that uses timer interrupts is always going to be tricky, because the source of the timer interrupts (e.g. a 6522) doesn'' t stop generating them when the ICE is single stepping. The BBC has this problem.
Generally what you have to do:
- special 1 (to disconnect IRQ)
- reset the system
- Single step/debug the main program as much as you like
When you want to test the interrupt handler you do:
- special 0 (to reconnect IRQ)
- step 1 (so the IRQ is seen by the CPU)
- special 1 (to disconnect IRQ)
- step 1 (to enter the IRQ handler)
- Single step/debug the IRQ handler as much as you like
Are you equippped to rebuild the Xilinx firmware from the github sources?
I'm happy to try making experimental changes for you on a branch in git, but it creates more work if I have to package and upload a binary release each time I do this.
Do you have a machine running Linux to hand?
Dave