master revision 1 voltage at PL8 outer pins rises

[arnoldemu]

Hi,

I mentioned this in another thread but I'm still a bit concerned.

On this master issue 1, I am measuring at north pin of PL8 a voltage which starts low and rises. I am comparing the voltage on this pin to the 0V spade nearby. What concerns me is I see the voltage steadily rising and every second or so it rises by an additional 0.3V ish and I have seen 8V at this pin.

I did see some 'gunk' nearby SK2 and PL12 and one of the VC1 terminals near closer to IC16. I am wondering if I have a break in a track or short in this area.

Would somebody be able to confirm for me what voltage should be seen on the north and south pins of PL8 without a battery pack connected after a minute of being switched on and is this voltage stable or does it increase?

Thank you.

[arnoldemu]

I can't read the issue 1 schematic which differs from issue 2 in this area.

On mine both gnd of PL8 go to R154 then to transistor 'Q4', the other pins of which are GND and R156. R156 then leads to +5V on north side of D8. South side of D8 seems to connect back to centre of PL8 via pads for D6 and D5 which are not connected.

Is there a better scan of issue 1 schematics around PL8?

Thank you.

[vexorg]

PL8 is the cmos battery connection, it shouldn't go above 5v ever on the centre pin, and the outer ones are definitiely ground.

What kind of meter do you have? is the battery good, I've found cheaper meter have unstabe readings as the battery gets low.

[arg]

This circuit with the J-FET is intended to prevent the battery being charged while the Master is powered on. It does so by leaving the positive end of the battery permanently connected to the 5V standby node (powered via a diode from the main 5V supply), and disconnects the negative end of the battery from GND.

Since the battery voltage is less than 5V, the outer pins of the connector should be somewhat above GND while the Master is powered on, then the FET turns on and allows the battery to power the RTC when 5V is off. It's hard to see how the centre pin could rise above 5V, even with a fault on there.

This is the circuit that (in)famously failed to work once the battery went flat, causing a few Masters to catch fire and the resulting recall to replace the original Lithium primary cells with packs of three Alkaline cells (and an in-line diode).

That J177 on the schematic is the part number for the FET:
https://www.mouser.co.uk/datasheet/2/67 ... 887866.pdf

[arnoldemu]

This circuit with the J-FET is intended to prevent the battery being charged while the Master is powered on. It does so by leaving the positive end of the battery permanently connected to the 5V standby node (powered via a diode from the main 5V supply), and disconnects the negative end of the battery from GND.

Since the battery voltage is less than 5V, the outer pins of the connector should be somewhat above GND while the Master is powered on, then the FET turns on and allows the battery to power the RTC when 5V is off. It's hard to see how the centre pin could rise above 5V, even with a fault on there.

This is the circuit that (in)famously failed to work once the battery went flat, causing a few Masters to catch fire and the resulting recall to replace the original Lithium primary cells with packs of three Alkaline cells (and an in-line diode).

That J177 on the schematic is the part number for the FET:
https://www.mouser.co.uk/datasheet/2/67 ... 887866.pdf

It is the outer 'GND' pins which are rising above 5V when measured against the GND spade nearby. I don't have any cable or battery connected because when I got it from storage the batteries had leaked and the cable broke off the battery carrier.

[arg]

It is the outer 'GND' pins which are rising above 5V when measured against the GND spade nearby. I don't have any cable or battery connected because when I got it from storage the batteries had leaked and the cable broke off the battery carrier.

I suspect that what you are measuring here isn't real.

Essentially those pins should be open-circuit while the power is on (the FET is gated off). There's not really any source of voltage to leak in to the pin from the on-board circuit, but equally there's no way for any externally-applied voltage to be conducted away. Maybe the combination of the meter and the capacitance of the Master circuit is rectifying 50Hz pickup on the wires?