Can anyone break down their expectations for `str r11, [r11, #0x10]!` for a dunce?

[ThomasHarte]

So that's:

• store word;
• with the value from r11;
• to address as per r11 with offset 10h added;
• preindexed, with write back.

i.e. it's specifically e5abb010h.

Given the data sheet's claim that "Data transfer instructions (LDR, STR) are aborted as though the instruction had not executed", questions prompted:

• does preindexed write back imply that if r11 is initially 0h then 10h will be written to [10h], or will the write back not occur until after the store?;
• if the former, does that imply some sort of special case is implemented in silicon given the need either not to update r11 in the register file until the transfer is complete, or else the need to restore the original value in case of a data abort?

I wonder if I've just confused myself into a corner here.

[minor addendum: I appreciate this isn't especially close to the remit for "32-bit acorn hardware" but it's a lot closer than to the other "32-bit acorn" sections, so apologies for that]

[bobcat]

There is a pseudo code description on PDF page 492 192 of https://documentation-service.arm.com/s ... 4dc521cd8b

It looks like this combination is UNPREDICTABLE i.e. don’t do it

Don’t have a machine handy to test what actually happens on any specific implementation.

[bobcat]

Looking at the block diagram on page 3-6 and remembering some detail about using the destination address register in an STM list, and how the behaviour depends on whether that register is the first one or not (page 3-29) I’d wager a pint that on ARM2/3 you get the old value of R11 written out before the updated value used for the address has been written back to register bank (and then out to write register…. ?). Maybe

https://www.chiark.greenend.org.uk/~the ... l-VLSI.pdf

[ThomasHarte]

It looks like this combination is UNPREDICTABLE i.e. don’t do it

I actually uncovered it while poking at RISC OS 3.11; check out the fragment around and including the tiny loop at 396be18h:

Code: Select all

0x396be18:   str r11, [r11, #0x10]!
            cmp r11, r14
            blt #0x396be18

Sadly I'm not organised enough to have a greater sense of the context here, having not found and being nowhere near the skill level necessary to produce any sort of full-length disassembly. But through simulation I'm pretty sure that code is on the startup path.

[sirbod]

"Implementation defined" is the expectation.

Off the top of my head:

ARMv2/v3 - it's a valid instruction and will do what you'd logically expect, ie [R11,#16]=R11
ARMv4 - probably deprecated, but I suspect will behave as ARMv2. It might store the pre-indexed R11 though, ie [R11,#16]=R11+16
ARMv5 - definitely deprecated and unpredictable, although in reality probably mirrors ARMv4 behaviour
ARMv6+ - probably generates an Abort