GAL16V8 as stopgap for dead video ULA

[KGE]

Hi,

My video ULA recently died in the BBC B here, no clock signals whatsoever, tried it in another BBC and no startup either.

I tried replacing it for testing with a GAL 16V8 generating the 4 clock signals(8/4/2/1 MHz), the CRT clock and the throughput/blanking of the SAA5050 RGB signals.

So far I managed to get the machine running albeit very unstable. The screen is somewhat glitchy and my cursor is one position off (to be expected).
But I do not understand why the computer is not running stable, it crashes after a few keystrokes for example.

The clock signals look fine on the oscilloscope, I tried altering the phase of CRTCLK (which in my GAL logic is synchronous and fixed to the 1 MHz clock signal output).
Even tried with an extra 16 MHz oscillator as input on the GAL but no diference. My understanding is that all clock stretching and such is done after the generation by the ULA.

Is there a detailed description of the ULA timing(s) including for example the phase between the clock signals available somewhere?

For now it would be ok just running in MODE 7 as that seemed the easiest mode to get going at first.

[KGE]

Small update:

I replaced the 4 bit GAL counter by a 74LS161 4 bit counter and at least I have MODE 7 working now.. Yeah...
Possibly my GAL is too slow or too weak to drive the signals of the BBC

[vexorg]

Do the tools allow you to work out the propagaion delays? or have you checked for any clock skew on the signals out with a scope?

[hoglet]

Is there a detailed description of the ULA timing(s) including for example the phase between the clock signals available somewhere?

Looking on a scope, the edges of the 1/2/4/8 MHz clocks (pins 4,5,6,7) are very tightly aligned.

The CTRC clock (pin 28) also looks very tightly aligned with the 1 or 2MHz clock depending on the screen mode.

By tighly aligned, I mean the phase difference is not really measurable on my 200MHz HP 54622D scope, so it should be less than 5ns.

So I'm surprised that your 16V8 PAL didn't work.

Can you post the source so I can take a look?

Dave

[KGE]

Is there a detailed description of the ULA timing(s) including for example the phase between the clock signals available somewhere?

Looking on a scope, the edges of the 1/2/4/8 MHz clocks (pins 4,5,6,7) are very tightly aligned.

The CTRC clock (pin 28) also looks very tightly aligned with the 1 or 2MHz clock depending on the screen mode.

By tighly aligned, I mean the phase difference is not really measurable on my 200MHz HP 54622D scope, so it should be less than 5ns.

So I'm surprised that your 16V8 PAL didn't work.

Can you post the source so I can take a look?

Dave

Hi Dave,

I will try and take some pictures of the signals, the GAL is still connected to the 16 MHz source so it is emitting the 4 clocks albeit unconnected to anything. The GAL does still handle the RGBin/out, DISEN and CURSOR signals. I will compare the phase with the clocks coming from the LS161. The source of the GAL 16V8 is on my Atari TT computer as that is the most reliable compiler and programmer I have for those older 16V8 and 20V8 chips. Alas the TT is not networked (yet). I can take a screenshot though as it is not a very big piece of source. I used an example 4 bit counter and stripped of the preset and reset logic. The GAL 16V8 I used is a 25 ns type. The 15 ns 16V8's I have are not recognized by the programmer. I tried two different brands of old 16V8 and both got me a glitchy and crashing Beeb

Gert

[KGE]

And just as I tried to merge the source of the 16V8 logic file into this message I see the mistake I made by simply copying the source from the example 4 bit counter..

At the top it says (sorry, it is in German) it only counts from 0 (0000) to 11 (1011) pfffff...

Code: Select all

Erstes Beispiel für einen aufwärts-vier-Bit-Zähler.

Zählfolge: 0 (0000) bis 11 (1011).

Alle Angaben in Logikgleichungen.
Realisierung nur mit Optimierung möglich!

%ID
   BBCULA

%TYP
   GAL16V8

%PINS
   CLK16 DISEN INVERT CURSOR NC NC BIN GIN RIN
   NC  CRTCLK ROUT GOUT BOUT CLK8 CLK4 CLK2 CLK1

%LOGIK

   CLK8 <- !CLK8; 
  
   CLK4 <- !CLK4 *  CLK8
   +	 CLK4 * !CLK8;
   
   CLK2 <- !CLK2 *  CLK4 *  CLK8
   +	 CLK2 * !CLK4
   + 	 CLK2 *  CLK4 * !CLK8;
   
   CLK1 <- !CLK1 *  CLK2 *  CLK4 *  CLK8
   +	  CLK1 * !CLK2
   + 	  CLK1 *  CLK2 * !CLK4
   +      CLK1 *  CLK2 *  CLK4 * !CLK8;

   ROUT = RIN + CURSOR * DISEN;
   GOUT = GIN + CURSOR * DISEN;
   BOUT = BIN + CURSOR * DISEN;
   
   CRTCLK <- !CLK1 *  CLK2 *  CLK4 *  CLK8
   +	  CLK1 * !CLK2
   + 	  CLK1 *  CLK2 * !CLK4
   +      CLK1 *  CLK2 *  CLK4 * !CLK8;
%END

[hoglet]

At the top it says (sorry, it is in German) it only counts from 0 (0000) to 11 (1011) pfffff...

That won't help, however...

Looking at the logic equations, I think they will count from 0 (0000) to 15 (1111)

So I think the comment is wrong, not the equations.

Dave

[KGE]

Well I found that the source got quite mangled and the compiler even 'optimized' one of the color outputs into the equations.. So I switched to GALasm and in their examples they also present a 4 bit counter. Slightly optimized as it seems. I tried this:

Code: Select all

GAL16V8    ; 4-Bit-Counter  first line : used GAL
BBC_ULA    ;                second line: any text (max. 8 char.)


CLK16 DISEN INVERT CURSOR NC NC BIN GIN RIN   GND
/OE   CRTCLK ROUT GOUT BOUT CLK8 CLK4 CLK2 CLK1  VCC

CLK8.R =  /CLK8


CLK4.R =  /CLK4 *  CLK8
       +  CLK4 * /CLK8


CLK2.R =  CLK2 * /CLK4
       +  CLK2 * /CLK8
       + /CLK2 *  CLK4 *  CLK8


CLK1.R =  CLK1 * /CLK2
       +  CLK1 * /CLK4
       +  CLK1 * /CLK8
       + /CLK1 *  CLK2 *  CLK4 *  CLK8

CRTCLK.R = CLK1 * /CLK2
       +  CLK1 * /CLK4
       +  CLK1 * /CLK8
       + /CLK1 *  CLK2 *  CLK4 *  CLK8


ROUT = RIN + CURSOR * DISEN
GOUT = GIN + CURSOR * DISEN
BOUT = BIN + CURSOR * DISEN

DESCRIPTION

this is a 4-Bit-Counter/divider for the BBC Micro

registered outputs are signed with the postfix .R

But so far the computer runs, no glitches on screen but the sound chip kicks in randomly and the system crashes again.. Maybe the CTRCLK equation is not correct, I tried to keep it the same as CLK1. hmm..

[KGE]

Tried connecting the CRTCLK directly at CLK1 and no glitches on screen but the BBC crashes all the time.
Scope images look ok, all clocks are there and as far as the scope can tell in the right phase and frequency.
Very weird..

[KGE]

For now I leave in the 74LS161 as base clock generator. I added a 74LS157 for selecting RGB between Teletext mode and the other modes.
The first GAL is now used for selecting the control register (a 74HC573) and merging the CURSOR, DISEN and RGB signals coming from the LS157 (I think I can use some unused outputs from the first GAL as inputs for the RGB selection so the LS157 is free for the next step: palette writing.

I placed a second GAL as a selection switch for the various clock signals 16/8/4/2 MHz for the upcoming shift register and also for selecting the CRTCLK 2/1 MHz and that seems to work fine. Teletext mode is ok (apart from the shifted cursor) and when selecting another mode the monitor sync correctly too.

The shift register is planned to be a third GAL, a 20V8 as I need more inputs then there are available on a 16V8 (8 databits, a 'latch' input and a shiftclock input and tri-state outputs).
I tried finding a suitable TTL parallel in/parallel out shift register as the intermediate outputs are needed also but found none in my collection. So another GAL it is. I will try and use a 8 kByte (massive overkill) SRAM (cache) as palette storage. I have loads of these and they should be fast enough. Writing the SRAM will be a challenge though.

[KGE]

First signs of high res life..

Using a GAL20V8 as shift register, no palette SRAM yet so just using the bits 1 3 5 7 as RGBF

I can not seem to find at what rate the shift register is to be 'fed' only that it shifts at 16 MHz (from the WiKi) which seems odd.

[hoglet]

I can not seem to find at what rate the shift register is to be 'fed' only that it shifts at 16 MHz (from the WiKi) which seems odd.

I think it will be fed 8 bits at a time at the CRTC clock rate (1MHz or 2MHz depending on the screen mode).

[KGE]

I can not seem to find at what rate the shift register is to be 'fed' only that it shifts at 16 MHz (from the WiKi) which seems odd.

I think it will be fed 8 bits at a time at the CRTC clock rate (1MHz or 2MHz depending on the screen mode).

Yes, that is what I thought too, I am using the CRTC clock signal as 'parallel load' signal and using the 16 MHz (or 8 or 4) as shift clock. But the whole screen is constantly active that way, lots of moving 'snow'. Maybe the shift clock should not be active constant as it is now but gated with DISEN for example.

[KGE]

like this

[maniacminer]

I thought he video output should be blanked when DISPEN isn't asserted? Are you committed to using GALs? I thought it would be good to have a 74 logic version of the video and serial ULAs to avoid stuff going obsolete.

[KGE]

I thought he video output should be blanked when DISPEN isn't asserted? Are you committed to using GALs? I thought it would be good to have a 74 logic version of the video and serial ULAs to avoid stuff going obsolete.

With an all TTL replacement the board space is going to be enormous, furthermore while I have some TTL chips lying around, for developing this kind of system GAL's are better suited because of the 5 Volt tolerance, speed and flexibility. And I have quite a bunch of them.. 16V8, 20V8 and some 22V10's
Also the development software for GAL does not take up Gigabytes of space..

[vexorg]

They have their place, though it's been 30+ years since I've used palasm

[KGE]

Making progress, all modes seem to work but still having some issues.
First the whole screen seems shifted a bit to the right and on the lefthand side there is a duplicated column from somewhere in the middle of the screen.
Palette writes are very time critical so it seems and is not fully stable yet.

The hardware consists of three GAL chips, 5 TTL chips and a fast SRAM chip

[KGE]

For the GAL equations and initial schematic
https://github.com/gertk64/BBC_Video_ULA

[dominicbeesley]

A pdf of the schematic might help people without kicad (or who are currently phone-bound like me) to join in.

This looks really interesting!

It look to me like you are close! I can't remember the exact is and outs but the funny stuff on the right can probably be fixed by delaying disen by one character cell spacing with a spare register if you have one. Without being able to see the schematic in not sure where that delay would need to be. You may need to delay the cursor too?

D

[KGE]

A pdf of the schematic might help people without kicad (or who are currently phone-bound like me) to join in.

This looks really interesting!

It look to me like you are close! I can't remember the exact is and outs but the funny stuff on the right can probably be fixed by delaying disen by one character cell spacing with a spare register if you have one. Without being able to see the schematic in not sure where that delay would need to be. You may need to delay the cursor too?

D

Schematic (Kicad sch) and the other files are visible now, I will add a PDF version also on github later this day.

Cursor delay is not yet implemented and is most visible/annoying in mode 7

For the shift register I have been looking at the 74x299 but it has combined in and outputs for parallel access so I am not sure if that is usable. All the other functions in the GAL's are non-registered so could be implemented in simple TTL

Delaying DISEN might be the solution for the shifting problem, will try something with that.

[tom_seddon]

I did some tests on a BBC B a while ago that suggested there is some kind of 1 byte delay for DISPEN input vs display output: https://github.com/tom-seddon/b2/issues/178 (I don't really know what I'm doing here, and I didn't get any further than doing the test. Still haven't got round to fixing my emulator)

--Tom

[e668ecp]

Hello,

Following this with interest. Once completed and working are the files going to be open source or do you intend producing replacement ula boards?

Thanks

[KGE]

Hello,

Following this with interest. Once completed and working are the files going to be open source or do you intend producing replacement ula boards?

Thanks

The project was literally a stopgap after my own BBC micro ULA died while testing/repairing some BBC components (like floppydrives and such) for a friend of mine. I have no intention for production but the source code of the GAL and a preliminary version of the schematic are available on the link posted above. Cursor displacement and a 'one column offset' is not yet inplemented but should be possible with a simple shift register or maybe even a simple D-latch. Feel free to try

[tricky]

Iirc, the 6845 keeps counting after the display is turned off, so reading it early will be about 2/3 of the way along the next line.

[KGE]

PDF of the schematic has been added to github

[Danto1]

I would try this diagram, but there is no jed file for the gal 20v8 system

[KGE]

I would try this diagram, but there is no jed file for the gal 20v8 system

Added

I have been experimenting with an extra 74LS74 as a 2 bit shift registers to delay the DISEN signal and got reasonable results. Not sure with what clock signal I have to clock it with to be perfect, probably propagation delay also messes exact timing up. Will update the circuit soon.

BTW, I used Galette as GAL assembler: https://github.com/simon-frankau/galette

[Danto1]

Great, thank you, because my mode 7 is broken in videoula

[maniacminer]

Great, thank you, because my mode 7 is broken in videoula

Are you sure? The output from the SAA5050 (Teletext IC) is just routed through the video ULA like a switch (with the cursor from the 6845 superimposed on top). Have you checked that IC15 is forwarding data and that IC6 is trying to output video? In all my Beebs I've not found one where the video ULA has failed with no MODE7 but the other modes work. However, I've had lots of other problems with similar symptoms. A common cause is a bad contact to pin#17 on the 6845, either a broken track, broken socket to board connection or a corroded pin/socket.