Combined VGA / Tube interface board for Atom

BigEd · Post by **BigEd** » Fri Feb 24, 2023 9:42 am

This is splendid stuff... if one of the better results at present is shimmer in the top lines, how about trying to cut over from variable length to correct length HSYNC a bit earlier - in the middle, or towards the end, of the blanking period? Is there a way to do that by counting or timing?

(When we say a few lines, do we mean a few pixel lines, or a few character lines?)

hoglet · Post by **hoglet** » Fri Feb 24, 2023 10:08 am

BigEd wrote: ↑Fri Feb 24, 2023 9:42 am (When we say a few lines, do we mean a few pixel lines, or a few character lines?)

This is very monitor specific...

They fall into at least four groups:
- affects zero active pixel lines
- affects ~5 active pixels lines (just the top of the 48 line top border, barely noticable as the border is solid(
- affects ~60 active pixel lines (all of the 48 line top border and the first character row)
- affects all of the screen (Ken's Lenova)

I suspect this is more of a continuum - the more agressive the correction, the more affect is has.

The other approach I tried was varying the clock for a complete frame. I might revisit this again if I can work out a way to detect the "in lock case". But using a different clock (+/- 780ppm) for the active lines would likely cause the monitor to mis-sample, or even loose lock.

I should say, all of these atrifacts only affects the ananlog VGA monitor. If RGBtoHDMI is used there is no issue. So even if we can't resolve them for analog VGA, the genlock still has some use!

Dave

BigEd · Post by **BigEd** » Fri Feb 24, 2023 10:57 am

Thanks Dave. When we say shimmering, does that more or less mean mis-sampling by the monitor? I'm thinking the monitor needs to have at least one PLL to try to track the timing of the incoming signal, and it will have its own dynamics, as to how it locks and how it tracks, and indeed how the start of each line is detected.

hoglet · Post by **hoglet** » Fri Feb 24, 2023 11:09 am

BigEd wrote: ↑Fri Feb 24, 2023 10:57 am Thanks Dave. When we say shimmering, does that more or less mean mis-sampling by the monitor?

Check out the first two videos in this post from Ken.
viewtopic.php?p=385618#p385618

It is mis-sampling, but it's mis-sampling inconsistently so it's far mor annoying.

BTW, I've not observed this on any of my monitors, what I'm seeing is far more benign.

Dace

BigEd · Post by **BigEd** » Fri Feb 24, 2023 12:15 pm

Thanks Dave - looks to me more like the pixels are moving, in other words the start of line is moving about, rather than the pixels being locked in position but sometimes picking up the wrong value.

Maybe the trailing edge of HSYNC isn't quite where the monitor expects, maybe the monitor's HSYNC PLL isn't quite happy with the signal it's getting. (Pure speculation!)

hoglet · Post by **hoglet** » Fri Feb 24, 2023 12:35 pm

BigEd wrote: ↑Fri Feb 24, 2023 12:15 pm Maybe the trailing edge of HSYNC isn't quite where the monitor expects, maybe the monitor's HSYNC PLL isn't quite happy with the signal it's getting. (Pure speculation!)

Indeed, I also suspect it's all down to the monitor's HSYNC PLL, and how quickly it responds to the +/- 780ppm variation in HSYNC period.

The best case being it responds almost immediately.

The worst case being it takes a while frame.

KenLowe · Post by **KenLowe** » Fri Feb 24, 2023 1:22 pm

hoglet wrote: ↑Fri Feb 24, 2023 8:57 am Have you tried tweaking RV1 on the Atom RGBtoHDMI board?

I hadn't, but I have now, and that's fixed it so thank you for the suggestion.

So, with that now sorted, and with the new crystal installed, everything seems to be working quite well now, both on PL4 and via PicoVGA - even with my Lenovo VGA monitor.

I might make a little PCB that allows me to break out VSYNC from PL4, whilst leaving a repeat set of pins available so you can still hook up a monitor to PL4. Right now I'm having to swap between genlocked PicoVGA and RGB2HDMi via PL4.

Do you think there is anything else we need to add to the PicoVGA board, or am I good to place another order?

hoglet · Post by **hoglet** » Fri Feb 24, 2023 2:48 pm

KenLowe wrote: ↑Fri Feb 24, 2023 1:22 pm Do you think there is anything else we need to add to the PicoVGA board, or am I good to place another order?

I've been wondering if there is another approach to the genlock implementation...

Instead of modulating the PIO clock, this would make use the Atom HSYNC signal. Every two VGA lines the PIO video_timing state machine would need to wait for the next falling HSYNC edge. You would end up much less jitter on the VGA timing signals than the current approach that changes the clock.

Some more details: The PIO clock is 250MHz (ish) so a 63.695us Atom line is ~15924 PIO clocks. Each extra PIO clock cycle is makes ~62ppm to the line direation, which is a pretty fine adjustment (compared to changing CLKDIV by one, which is a 780ppm change). And because this is done in the PIO, it's done for each and every line.

I have no idea if it's possible to hack this into the current scanvideo code. I suspect not, as it's a big change to how it works currently. It may also introduce noticable sampling noise.

And, of course, it would also need a second level shifter, because Atom VSYNC is still needed.

Maybe this is something for a future design iteration?

Dave

KenLowe · Post by **KenLowe** » Fri Feb 24, 2023 3:34 pm

hoglet wrote: ↑Fri Feb 24, 2023 2:48 pm And, of course, it would also need a second level shifter, because Atom VSYNC is still needed.

Maybe this is something for a future design iteration?

I could add that in now. I should have space around the Pico to fit it in. I'd need to ditch the Pico nTUBE signal, as discussed earlier, to free up a Pico PIO. It shouldn't take too much effort. TBH, I'd rather do this now rather than wish I'd done it after placing the order!

KenLowe · Post by **KenLowe** » Sat Feb 25, 2023 10:37 am

Ok. I got a little bit distracted yesterday, but here's the latest board layout with HSYNC input and associated level shifter added. I've stripped out the Pico_Tube signal and the associated jumper block to make room for this. I renumbered the remaining jumper blocks to keep everything in sequence. This means that I also had to update the jumper descriptors on the rear of the PCB. Finally, I've also tidied up some of the other component layout around the Pico, and renumbered the resistors. Does that all look reasonable? Any other final requests / suggestions?

: Updated schematic - with HSYNC added

: PCB front view

: PCB rear view

: 3D render

Atom_VGA_Tube_Combo.pdf: Updated schematic - pdf copy; (253.74 KiB) Downloaded 17 times

hoglet · Post by **hoglet** » Sat Feb 25, 2023 10:49 am

KenLowe wrote: ↑Sat Feb 25, 2023 10:37 am Does that all look reasonable? Any other final requests / suggestions?

That all looks great Ken.

One last thing to check about CN5. Will the Dupont connectors/cables foul anything on your PiTubeDirect level shifter, or is there plenly of space. I'm thinking particularly the lower pin. Sorry, stupid question, the adjacent connector is for a external Tube cable.

Dave

KenLowe · Post by **KenLowe** » Sat Feb 25, 2023 11:44 am

hoglet wrote: ↑Sat Feb 25, 2023 10:49 am One last thing to check about CN5. Will the Dupont connectors/cables foul anything on your PiTubeDirect level shifter, or is there plenly of space. I'm thinking particularly the lower pin. Sorry, stupid question, the adjacent connector is for a external Tube cable.

That is a valid question. If you want to, you can connect PiTubeDirect (or any other Tube device, like Matchbox) directly to this header. There shouldn't be any clash with PiTubeDirect, but I'm less certain about the Matchbox because I don't have one to check against.

The photo below shows PiTubeDirect connected to one of my V1 boards. Whilst CN5 isn't located next the Tube connector on this revision of board, you can see that there should be sufficient space to connect the dupont wires on the V2 board. Although you can't see it in the photo, this mock up has highlighted that the Pi USB sockets, which sit proud of the Pi PCB outline, clash slightly with the PicoVGA PCB. I might actually take a slight nibble out of the PicoVGA PCB to fix that.

It would be worth checking that there isn't any clash with the Matchbox Co-Pro, as that would probably be the most likely reason to use the header. I've found a photo on the site that shows the Matchbox plugged into one of your original Atom Tube interface PCBs, and on inspection I think it would be ok, but would certainly be worth confirming. It's perhaps got the potential to clash - particularly if the 40 pin socket on the Matchbox PCB has been soldered flush with the underside of the Matchbox PCB?

: PiTubeDirect connected to external port of PicoVGA board

KenLowe · Post by **KenLowe** » Sat Feb 25, 2023 1:46 pm

KenLowe wrote: ↑Sat Feb 25, 2023 11:44 am I might actually take a slight nibble out of the PicoVGA PCB to fix that.

That turned out to be quite a useful exercise, as it highlighted another issue. For some reason my board constraints weren't quite right, and I was allowing copper all the way up to the board edge. JLC require a minimum gap of 0.2mm. So that's now also fixed.

: Board layout, with cutouts for external Pi USB and HDMI connectors

hoglet · Post by **hoglet** » Sat Feb 25, 2023 3:31 pm

KenLowe wrote: ↑Sat Feb 25, 2023 11:44 am It would be worth checking that there isn't any clash with the Matchbox Co-Pro, as that would probably be the most likely reason to use the header. I've found a photo on the site that shows the Matchbox plugged into one of your original Atom Tube interface PCBs, and on inspection I think it would be ok, but would certainly be worth confirming. It's perhaps got the potential to clash - particularly if the 40 pin socket on the Matchbox PCB has been soldered flush with the underside of the Matchbox PCB?

The connector is flush, so the boards are offset quite a bit vertically:

Good spot with the USB connector. On that note, how close is the USB connector/cable going to end up to the Atom case pillar?

Dave

KenLowe · Post by **KenLowe** » Sat Feb 25, 2023 4:17 pm

Ok. I assume that's the Matchbox on the RHS of that photo, with the underside of the Matchbox PCB flush with the upperside of the host PCB?

If that's the case then there may well be a clash, but I'm hesitant to make any changes to relocate this header. That would be a major change to the board layout. If using a Matchbox then I guess there would be the option of using a vertical header instead of the horizontal header, or perhaps place a horizontal header on the underside of the PCB, possibly turned by 90 degrees (1x02 instead of 2x01) so it's pointing towards PL4. You might actually need to use a 2x02 header with the lower set of pins removed to get enough height to clear the soldered pins of the 40 pin header.

The board clears the case pillar quite comfortably. The 40 pin Tube header is further inboard as well, giving more room for wider Tube boards to be installed too.

: Sync Header on rear of PCB.

: Space between edge of PicoVGA board and Atom support pillar

hoglet · Post by **hoglet** » Sat Feb 25, 2023 4:42 pm

KenLowe wrote: ↑Sat Feb 25, 2023 4:17 pm Ok. I assume that's the Matchbox on the RHS of that photo, with the underside of the Matchbox PCB flush with the upperside of the host PCB?

Yes.

KenLowe wrote: ↑Sat Feb 25, 2023 4:17 pm If that's the case then there may well be a clash, but I'm hesitant to make any changes to relocate this header.

That's fine with me.

As you say, there are various options to work around this.

hoglet · Post by **hoglet** » Sat Feb 25, 2023 6:30 pm

Ken,

Here's another genlock AtomVGA build for you to test:

8f35be96.zip: (31.16 KiB) Downloaded 16 times

This now works completely differently, and is hopefully an improvement

Changes include:
- the nominal clock should be much more accurate (to within 3ppm if the Pico clock is spot on)
- the GENLOCK command parameter is now just 0 (off) and 1 (on)
- there is a new Genlock PIO state machine to accurately track the offset between the VGA VSync and the Atom Frame Sync
- the genlock PLL is now much more sophisticated and has several thresholds (coarse, locked and unlocked)
- the clock divider correction is now applied for a complete frame rather than just a few lines
- it should always lock within a couple of seconds
- it locks on my Atom with 300ppm crystal error

This is working well on all of the monitors I have tried, apart from an old Samsung Syncmaster 711, which now locks up. The judder/wobble is gone on all the other monitors.

I wrote a C program to explore how clock we could get to the nominal Atom clock with every possible system clock, and then display the results that are within 100ppm:

Code: Select all

191.142857 (refdiv = 2; fbdiv = 223, vco = 1338 pd1 = 7, pd2 = 1, clkdiv = 0x3ce ( 974), ppm =  12.79
193.500000 (refdiv = 1; fbdiv = 129, vco = 1548 pd1 = 4, pd2 = 2, clkdiv = 0x3da ( 986), ppm =   1.42
193.500000 (refdiv = 2; fbdiv = 129, vco =  774 pd1 = 4, pd2 = 1, clkdiv = 0x3da ( 986), ppm =   1.42
193.500000 (refdiv = 2; fbdiv = 258, vco = 1548 pd1 = 4, pd2 = 2, clkdiv = 0x3da ( 986), ppm =   1.42
193.714286 (refdiv = 1; fbdiv = 113, vco = 1356 pd1 = 7, pd2 = 1, clkdiv = 0x3db ( 987), ppm = -91.70
193.714286 (refdiv = 2; fbdiv = 226, vco = 1356 pd1 = 7, pd2 = 1, clkdiv = 0x3db ( 987), ppm = -91.70
198.000000 (refdiv = 1; fbdiv = 132, vco = 1584 pd1 = 4, pd2 = 2, clkdiv = 0x3f1 (1009), ppm =  70.57
198.000000 (refdiv = 1; fbdiv =  66, vco =  792 pd1 = 4, pd2 = 1, clkdiv = 0x3f1 (1009), ppm =  70.57
198.000000 (refdiv = 1; fbdiv =  99, vco = 1188 pd1 = 6, pd2 = 1, clkdiv = 0x3f1 (1009), ppm =  70.57
198.000000 (refdiv = 2; fbdiv = 132, vco =  792 pd1 = 4, pd2 = 1, clkdiv = 0x3f1 (1009), ppm =  70.57
198.000000 (refdiv = 2; fbdiv = 165, vco =  990 pd1 = 5, pd2 = 1, clkdiv = 0x3f1 (1009), ppm =  70.57
198.000000 (refdiv = 2; fbdiv = 198, vco = 1188 pd1 = 6, pd2 = 1, clkdiv = 0x3f1 (1009), ppm =  70.57
198.000000 (refdiv = 2; fbdiv = 231, vco = 1386 pd1 = 7, pd2 = 1, clkdiv = 0x3f1 (1009), ppm =  70.57
198.000000 (refdiv = 2; fbdiv = 264, vco = 1584 pd1 = 4, pd2 = 2, clkdiv = 0x3f1 (1009), ppm =  70.57
199.000000 (refdiv = 2; fbdiv = 199, vco = 1194 pd1 = 6, pd2 = 1, clkdiv = 0x3f6 (1014), ppm = -24.06
199.200000 (refdiv = 1; fbdiv =  83, vco =  996 pd1 = 5, pd2 = 1, clkdiv = 0x3f7 (1015), ppm = -42.88
199.200000 (refdiv = 2; fbdiv = 166, vco =  996 pd1 = 5, pd2 = 1, clkdiv = 0x3f7 (1015), ppm = -42.88
200.571429 (refdiv = 1; fbdiv = 117, vco = 1404 pd1 = 7, pd2 = 1, clkdiv = 0x3fe (1022), ppm = -31.09
200.571429 (refdiv = 2; fbdiv = 234, vco = 1404 pd1 = 7, pd2 = 1, clkdiv = 0x3fe (1022), ppm = -31.09
207.428571 (refdiv = 1; fbdiv = 121, vco = 1452 pd1 = 7, pd2 = 1, clkdiv = 0x421 (1057), ppm =  25.52
207.428571 (refdiv = 2; fbdiv = 242, vco = 1452 pd1 = 7, pd2 = 1, clkdiv = 0x421 (1057), ppm =  25.52
208.800000 (refdiv = 1; fbdiv =  87, vco = 1044 pd1 = 5, pd2 = 1, clkdiv = 0x428 (1064), ppm =  36.39
208.800000 (refdiv = 2; fbdiv = 174, vco = 1044 pd1 = 5, pd2 = 1, clkdiv = 0x428 (1064), ppm =  36.39
209.000000 (refdiv = 2; fbdiv = 209, vco = 1254 pd1 = 6, pd2 = 1, clkdiv = 0x429 (1065), ppm =  18.40
210.000000 (refdiv = 1; fbdiv = 105, vco = 1260 pd1 = 6, pd2 = 1, clkdiv = 0x42e (1070), ppm = -71.02
210.000000 (refdiv = 1; fbdiv =  70, vco =  840 pd1 = 4, pd2 = 1, clkdiv = 0x42e (1070), ppm = -71.02
210.000000 (refdiv = 2; fbdiv = 140, vco =  840 pd1 = 4, pd2 = 1, clkdiv = 0x42e (1070), ppm = -71.02
210.000000 (refdiv = 2; fbdiv = 175, vco = 1050 pd1 = 5, pd2 = 1, clkdiv = 0x42e (1070), ppm = -71.02
210.000000 (refdiv = 2; fbdiv = 210, vco = 1260 pd1 = 6, pd2 = 1, clkdiv = 0x42e (1070), ppm = -71.02
210.000000 (refdiv = 2; fbdiv = 245, vco = 1470 pd1 = 7, pd2 = 1, clkdiv = 0x42e (1070), ppm = -71.02
214.285714 (refdiv = 1; fbdiv = 125, vco = 1500 pd1 = 7, pd2 = 1, clkdiv = 0x444 (1092), ppm =  78.50
214.285714 (refdiv = 2; fbdiv = 250, vco = 1500 pd1 = 7, pd2 = 1, clkdiv = 0x444 (1092), ppm =  78.50
214.500000 (refdiv = 2; fbdiv = 143, vco =  858 pd1 = 4, pd2 = 1, clkdiv = 0x445 (1093), ppm =  -5.67
216.857143 (refdiv = 2; fbdiv = 253, vco = 1518 pd1 = 7, pd2 = 1, clkdiv = 0x451 (1105), ppm = -15.62
219.000000 (refdiv = 1; fbdiv =  73, vco =  876 pd1 = 4, pd2 = 1, clkdiv = 0x45c (1116), ppm =  56.99
219.000000 (refdiv = 2; fbdiv = 146, vco =  876 pd1 = 4, pd2 = 1, clkdiv = 0x45c (1116), ppm =  56.99
219.000000 (refdiv = 2; fbdiv = 219, vco = 1314 pd1 = 6, pd2 = 1, clkdiv = 0x45c (1116), ppm =  56.99
219.600000 (refdiv = 2; fbdiv = 183, vco = 1098 pd1 = 5, pd2 = 1, clkdiv = 0x45f (1119), ppm =   5.58
220.000000 (refdiv = 1; fbdiv = 110, vco = 1320 pd1 = 6, pd2 = 1, clkdiv = 0x461 (1121), ppm = -28.55
220.000000 (refdiv = 2; fbdiv = 220, vco = 1320 pd1 = 6, pd2 = 1, clkdiv = 0x461 (1121), ppm = -28.55
220.800000 (refdiv = 1; fbdiv =  92, vco = 1104 pd1 = 5, pd2 = 1, clkdiv = 0x465 (1125), ppm = -96.42
220.800000 (refdiv = 2; fbdiv = 184, vco = 1104 pd1 = 5, pd2 = 1, clkdiv = 0x465 (1125), ppm = -96.42
223.714286 (refdiv = 2; fbdiv = 261, vco = 1566 pd1 = 7, pd2 = 1, clkdiv = 0x474 (1140), ppm =  36.39
226.285714 (refdiv = 1; fbdiv = 132, vco = 1584 pd1 = 7, pd2 = 1, clkdiv = 0x481 (1153), ppm = -53.32
226.285714 (refdiv = 2; fbdiv = 264, vco = 1584 pd1 = 7, pd2 = 1, clkdiv = 0x481 (1153), ppm = -53.32
229.000000 (refdiv = 2; fbdiv = 229, vco = 1374 pd1 = 6, pd2 = 1, clkdiv = 0x48f (1167), ppm =  92.21
229.200000 (refdiv = 2; fbdiv = 191, vco = 1146 pd1 = 5, pd2 = 1, clkdiv = 0x490 (1168), ppm =  75.76
230.000000 (refdiv = 1; fbdiv = 115, vco = 1380 pd1 = 6, pd2 = 1, clkdiv = 0x494 (1172), ppm =  10.24
230.000000 (refdiv = 2; fbdiv = 230, vco = 1380 pd1 = 6, pd2 = 1, clkdiv = 0x494 (1172), ppm =  10.24
230.400000 (refdiv = 1; fbdiv =  96, vco = 1152 pd1 = 5, pd2 = 1, clkdiv = 0x496 (1174), ppm = -22.35
230.400000 (refdiv = 2; fbdiv = 192, vco = 1152 pd1 = 5, pd2 = 1, clkdiv = 0x496 (1174), ppm = -22.35
231.000000 (refdiv = 1; fbdiv =  77, vco =  924 pd1 = 4, pd2 = 1, clkdiv = 0x499 (1177), ppm = -71.02
231.000000 (refdiv = 2; fbdiv = 154, vco =  924 pd1 = 4, pd2 = 1, clkdiv = 0x499 (1177), ppm = -71.02
231.000000 (refdiv = 2; fbdiv = 231, vco = 1386 pd1 = 6, pd2 = 1, clkdiv = 0x499 (1177), ppm = -71.02
235.500000 (refdiv = 2; fbdiv = 157, vco =  942 pd1 = 4, pd2 = 1, clkdiv = 0x4b0 (1200), ppm = -11.50
240.000000 (refdiv = 1; fbdiv = 100, vco = 1200 pd1 = 5, pd2 = 1, clkdiv = 0x4c7 (1223), ppm =  45.79
240.000000 (refdiv = 1; fbdiv = 120, vco = 1440 pd1 = 6, pd2 = 1, clkdiv = 0x4c7 (1223), ppm =  45.79
240.000000 (refdiv = 1; fbdiv =  80, vco =  960 pd1 = 4, pd2 = 1, clkdiv = 0x4c7 (1223), ppm =  45.79
240.000000 (refdiv = 2; fbdiv = 160, vco =  960 pd1 = 4, pd2 = 1, clkdiv = 0x4c7 (1223), ppm =  45.79
240.000000 (refdiv = 2; fbdiv = 200, vco = 1200 pd1 = 5, pd2 = 1, clkdiv = 0x4c7 (1223), ppm =  45.79
240.000000 (refdiv = 2; fbdiv = 240, vco = 1440 pd1 = 6, pd2 = 1, clkdiv = 0x4c7 (1223), ppm =  45.79
241.000000 (refdiv = 2; fbdiv = 241, vco = 1446 pd1 = 6, pd2 = 1, clkdiv = 0x4cc (1228), ppm = -32.25
241.200000 (refdiv = 2; fbdiv = 201, vco = 1206 pd1 = 5, pd2 = 1, clkdiv = 0x4cd (1229), ppm = -47.78
250.000000 (refdiv = 1; fbdiv = 125, vco = 1500 pd1 = 6, pd2 = 1, clkdiv = 0x4fa (1274), ppm =  78.50
250.000000 (refdiv = 2; fbdiv = 125, vco =  750 pd1 = 3, pd2 = 1, clkdiv = 0x4fa (1274), ppm =  78.50
250.000000 (refdiv = 2; fbdiv = 250, vco = 1500 pd1 = 6, pd2 = 1, clkdiv = 0x4fa (1274), ppm =  78.50
250.800000 (refdiv = 2; fbdiv = 209, vco = 1254 pd1 = 5, pd2 = 1, clkdiv = 0x4fe (1278), ppm =  18.40
251.000000 (refdiv = 2; fbdiv = 251, vco = 1506 pd1 = 6, pd2 = 1, clkdiv = 0x4ff (1279), ppm =   3.44
252.000000 (refdiv = 1; fbdiv = 105, vco = 1260 pd1 = 5, pd2 = 1, clkdiv = 0x504 (1284), ppm = -71.02
252.000000 (refdiv = 1; fbdiv = 126, vco = 1512 pd1 = 6, pd2 = 1, clkdiv = 0x504 (1284), ppm = -71.02
252.000000 (refdiv = 1; fbdiv =  63, vco =  756 pd1 = 3, pd2 = 1, clkdiv = 0x504 (1284), ppm = -71.02
252.000000 (refdiv = 1; fbdiv =  84, vco = 1008 pd1 = 4, pd2 = 1, clkdiv = 0x504 (1284), ppm = -71.02
252.000000 (refdiv = 2; fbdiv = 126, vco =  756 pd1 = 3, pd2 = 1, clkdiv = 0x504 (1284), ppm = -71.02
252.000000 (refdiv = 2; fbdiv = 168, vco = 1008 pd1 = 4, pd2 = 1, clkdiv = 0x504 (1284), ppm = -71.02
252.000000 (refdiv = 2; fbdiv = 210, vco = 1260 pd1 = 5, pd2 = 1, clkdiv = 0x504 (1284), ppm = -71.02
252.000000 (refdiv = 2; fbdiv = 252, vco = 1512 pd1 = 6, pd2 = 1, clkdiv = 0x504 (1284), ppm = -71.02
256.500000 (refdiv = 2; fbdiv = 171, vco = 1026 pd1 = 4, pd2 = 1, clkdiv = 0x51b (1307), ppm = -16.37
260.400000 (refdiv = 2; fbdiv = 217, vco = 1302 pd1 = 5, pd2 = 1, clkdiv = 0x52f (1327), ppm =  79.70
261.000000 (refdiv = 1; fbdiv =  87, vco = 1044 pd1 = 4, pd2 = 1, clkdiv = 0x532 (1330), ppm =  36.39
261.000000 (refdiv = 2; fbdiv = 174, vco = 1044 pd1 = 4, pd2 = 1, clkdiv = 0x532 (1330), ppm =  36.39
261.000000 (refdiv = 2; fbdiv = 261, vco = 1566 pd1 = 6, pd2 = 1, clkdiv = 0x532 (1330), ppm =  36.39
261.600000 (refdiv = 1; fbdiv = 109, vco = 1308 pd1 = 5, pd2 = 1, clkdiv = 0x535 (1333), ppm =  -6.72
261.600000 (refdiv = 2; fbdiv = 218, vco = 1308 pd1 = 5, pd2 = 1, clkdiv = 0x535 (1333), ppm =  -6.72
262.000000 (refdiv = 1; fbdiv = 131, vco = 1572 pd1 = 6, pd2 = 1, clkdiv = 0x537 (1335), ppm = -35.35
262.000000 (refdiv = 2; fbdiv = 131, vco =  786 pd1 = 3, pd2 = 1, clkdiv = 0x537 (1335), ppm = -35.35
262.000000 (refdiv = 2; fbdiv = 262, vco = 1572 pd1 = 6, pd2 = 1, clkdiv = 0x537 (1335), ppm = -35.35
262.800000 (refdiv = 2; fbdiv = 219, vco = 1314 pd1 = 5, pd2 = 1, clkdiv = 0x53b (1339), ppm = -92.36
265.500000 (refdiv = 2; fbdiv = 177, vco = 1062 pd1 = 4, pd2 = 1, clkdiv = 0x549 (1353), ppm =  87.37
271.200000 (refdiv = 1; fbdiv = 113, vco = 1356 pd1 = 5, pd2 = 1, clkdiv = 0x566 (1382), ppm =  53.03
271.200000 (refdiv = 2; fbdiv = 226, vco = 1356 pd1 = 5, pd2 = 1, clkdiv = 0x566 (1382), ppm =  53.03
272.000000 (refdiv = 1; fbdiv =  68, vco =  816 pd1 = 3, pd2 = 1, clkdiv = 0x56a (1386), ppm =  -2.31
272.000000 (refdiv = 2; fbdiv = 136, vco =  816 pd1 = 3, pd2 = 1, clkdiv = 0x56a (1386), ppm =  -2.31
272.400000 (refdiv = 2; fbdiv = 227, vco = 1362 pd1 = 5, pd2 = 1, clkdiv = 0x56c (1388), ppm = -29.86
273.000000 (refdiv = 1; fbdiv =  91, vco = 1092 pd1 = 4, pd2 = 1, clkdiv = 0x56f (1391), ppm = -71.02
273.000000 (refdiv = 2; fbdiv = 182, vco = 1092 pd1 = 4, pd2 = 1, clkdiv = 0x56f (1391), ppm = -71.02
277.500000 (refdiv = 2; fbdiv = 185, vco = 1110 pd1 = 4, pd2 = 1, clkdiv = 0x586 (1414), ppm = -20.51
282.000000 (refdiv = 1; fbdiv =  94, vco = 1128 pd1 = 4, pd2 = 1, clkdiv = 0x59d (1437), ppm =  28.39
282.000000 (refdiv = 2; fbdiv = 141, vco =  846 pd1 = 3, pd2 = 1, clkdiv = 0x59d (1437), ppm =  28.39
282.000000 (refdiv = 2; fbdiv = 188, vco = 1128 pd1 = 4, pd2 = 1, clkdiv = 0x59d (1437), ppm =  28.39
282.000000 (refdiv = 2; fbdiv = 235, vco = 1410 pd1 = 5, pd2 = 1, clkdiv = 0x59d (1437), ppm =  28.39
283.200000 (refdiv = 1; fbdiv = 118, vco = 1416 pd1 = 5, pd2 = 1, clkdiv = 0x5a3 (1443), ppm = -51.22
283.200000 (refdiv = 2; fbdiv = 236, vco = 1416 pd1 = 5, pd2 = 1, clkdiv = 0x5a3 (1443), ppm = -51.22
286.500000 (refdiv = 2; fbdiv = 191, vco = 1146 pd1 = 4, pd2 = 1, clkdiv = 0x5b4 (1460), ppm =  75.76
291.600000 (refdiv = 2; fbdiv = 243, vco = 1458 pd1 = 5, pd2 = 1, clkdiv = 0x5ce (1486), ppm =  82.81
292.000000 (refdiv = 1; fbdiv =  73, vco =  876 pd1 = 3, pd2 = 1, clkdiv = 0x5d0 (1488), ppm =  56.99
292.000000 (refdiv = 2; fbdiv = 146, vco =  876 pd1 = 3, pd2 = 1, clkdiv = 0x5d0 (1488), ppm =  56.99
292.800000 (refdiv = 1; fbdiv = 122, vco = 1464 pd1 = 5, pd2 = 1, clkdiv = 0x5d4 (1492), ppm =   5.58
292.800000 (refdiv = 2; fbdiv = 244, vco = 1464 pd1 = 5, pd2 = 1, clkdiv = 0x5d4 (1492), ppm =   5.58
294.000000 (refdiv = 1; fbdiv =  98, vco = 1176 pd1 = 4, pd2 = 1, clkdiv = 0x5da (1498), ppm = -71.02
294.000000 (refdiv = 2; fbdiv = 147, vco =  882 pd1 = 3, pd2 = 1, clkdiv = 0x5da (1498), ppm = -71.02
294.000000 (refdiv = 2; fbdiv = 196, vco = 1176 pd1 = 4, pd2 = 1, clkdiv = 0x5da (1498), ppm = -71.02
294.000000 (refdiv = 2; fbdiv = 245, vco = 1470 pd1 = 5, pd2 = 1, clkdiv = 0x5da (1498), ppm = -71.02
298.500000 (refdiv = 2; fbdiv = 199, vco = 1194 pd1 = 4, pd2 = 1, clkdiv = 0x5f1 (1521), ppm = -24.06
302.000000 (refdiv = 2; fbdiv = 151, vco =  906 pd1 = 3, pd2 = 1, clkdiv = 0x603 (1539), ppm =  83.70
302.400000 (refdiv = 1; fbdiv = 126, vco = 1512 pd1 = 5, pd2 = 1, clkdiv = 0x605 (1541), ppm =  58.77
302.400000 (refdiv = 2; fbdiv = 252, vco = 1512 pd1 = 5, pd2 = 1, clkdiv = 0x605 (1541), ppm =  58.77
303.000000 (refdiv = 1; fbdiv = 101, vco = 1212 pd1 = 4, pd2 = 1, clkdiv = 0x608 (1544), ppm =  21.50
303.000000 (refdiv = 2; fbdiv = 202, vco = 1212 pd1 = 4, pd2 = 1, clkdiv = 0x608 (1544), ppm =  21.50
303.600000 (refdiv = 2; fbdiv = 253, vco = 1518 pd1 = 5, pd2 = 1, clkdiv = 0x60b (1547), ppm = -15.62
304.000000 (refdiv = 1; fbdiv =  76, vco =  912 pd1 = 3, pd2 = 1, clkdiv = 0x60d (1549), ppm = -40.28
304.000000 (refdiv = 2; fbdiv = 152, vco =  912 pd1 = 3, pd2 = 1, clkdiv = 0x60d (1549), ppm = -40.28
304.800000 (refdiv = 1; fbdiv = 127, vco = 1524 pd1 = 5, pd2 = 1, clkdiv = 0x611 (1553), ppm = -89.42
304.800000 (refdiv = 2; fbdiv = 254, vco = 1524 pd1 = 5, pd2 = 1, clkdiv = 0x611 (1553), ppm = -89.42
307.500000 (refdiv = 2; fbdiv = 205, vco = 1230 pd1 = 4, pd2 = 1, clkdiv = 0x61f (1567), ppm =  65.74
best ppm =   1.42 at clock 193.500000, clkdiv 986

This is the one I ended up using:

Code: Select all

251.000000 (refdiv = 2; fbdiv = 251, vco = 1506 pd1 = 6, pd2 = 1, clkdiv = 0x4ff (1279), ppm =   3.44

It has a PLL refdiv value of 2, which isn't officically support by the SDK, but I was able to get this working.

There is also some debug logging on the Pico serial port that looks like:

Code: Select all

U -5579 -3
U -5572 -3
U -5530 -3
U -5487 -3
U -5445 -3
U -5402 -3
U -5360 -3
U -5318 -3
U -5275 -3
U -5233 -3
U -5190 -3
U -5148 -3
U -5105 -3
U -5063 -3
U -5020 -3
U -4978 -3
U -4935 -3
U -4893 -3
U -4850 -3
U -4808 -3
U -4765 -3
U -4723 -3
U -4681 -3
U -4638 -3
U -4596 -3
U -4553 -3
U -4511 -3
U -4468 -3
U -4426 -3
U -4383 -3
U -4341 -3
U -4298 -3
U -4256 -3
U -4213 -3
U -4171 -3
U -4128 -3
U -4086 -3
U -4044 -3
U -4001 -3
U -3959 -3
U -3916 -3
U -3874 -3
U -3831 -3
U -3789 -3
U -3746 -3
U -3704 -3
U -3661 -3
U -3619 -3
U -3576 -3
U -3534 -3
U -3492 -3
U -3449 -3
U -3407 -3
U -3364 -3
U -3322 -3
U -3279 -3
U -3237 -3
U -3194 -3
U -3152 -3
U -3109 -3
U -3067 -3
U -3024 -3
U -2982 -3
U -2940 -3
U -2897 -3
U -2855 -3
U -2812 -3
U -2770 -3
U -2727 -3
U -2685 -3
U -2642 -3
U -2600 -3
U -2557 -3
U -2515 -3
U -2472 -3
U -2430 -3
U -2388 -3
U -2345 -3
U -2303 -3
U -2260 -3
U -2218 -3
U -2175 -3
U -2133 -3
U -2090 -3
U -2048 -3
U -2005 -3
U -1963 -3
U -1920 -3
U -1878 -3
U -1836 -3
U -1793 -3
U -1751 -3
U -1708 -3
U -1666 -3
U -1623 -3
U -1581 -3
U -1538 -3
U -1496 -3
U -1453 -3
U -1411 -3
U -1369 -3
U -1326 -3
U -1284 -3
U -1241 -3
U -1199 -3
U -1156 -3
U -1114 -3
U -1071 -3
U -1029 -3
U -986 -3
U -944 -3
U -901 -3
U -859 -3
U -817 -3
U -774 -3
U -732 -3
U -689 -3
U -647 -3
U -604 -3
U -562 -3
U -519 -3
U -477 -3
U -434 -3
U -392 -3
U -349 -3
U -307 -3
U -265 -3
U -222 -3
U -180 -3
U -137 -3
U -95 -1
U -55 -1
U -38 -1
U -22 -1
L -6 0
L 9 0
L 12 0
L 15 0
L 19 0
L 22 0
L 25 0
L 28 0
L 31 0
U 34 1
U 36 1
U 26 1
U 16 1
L 7 0
L -2 0
L 1 0
L 4 0
L 7 0
L 10 0
L 14 0
L 17 0
L 20 0
L 23 0
L 26 0
L 29 0
U 33 1
U 35 1
U 25 1
U 15 1
L 5 0
L -4 0
L -1 0
L 2 0
L 6 0
L 9 0
L 12 0
L 15 0
L 18 0
L 21 0
L 25 0
L 28 0
L 31 0
U 34 1
U 36 1
U 26 1
U 16 1
L 6 0
L -3 0
L 1 0
L 4 0
L 7 0
L 10 0
L 13 0
L 16 0
L 20 0
L 23 0
L 26 0
L 29 0
L 32 0
U 35 1
U 37 1
U 27 1
U 18 1
U 8 1
L -2 0
L -11 0
L -8 0
L -5 0
L -2 0
L 2 0
L 5 0
L 8 0
L 11 0
L 14 0
L 17 0
L 21 0
L 24 0
L 27 0
L 30 0
U 33 1
U 35 1
U 25 1
U 15 1
L 5 0
L -3 0
L 0 0
L 3 0
L 6 0
L 9 0
L 12 0
L 16 0
L 19 0
L 22 0
L 25 0
L 28 0
L 31 0

This is outputting one line per frame, showing locked/unlocked, the vsync offset (in us) and the current divider delta.

Very interested to see how you get on with this...

Dave

KenLowe · Post by **KenLowe** » Sat Feb 25, 2023 7:36 pm

To get genlock I now need to increase CLKDIV to around 1278.

However, when I do that, I now see a slight pulsing effect on the Lenovo monitor. I think the characters grows slightly, and then jump back to their original size, and this repeats about twice a second.

The Dell monitor works fine. There's still no noticeable shimmering or pulsing.

hoglet · Post by **hoglet** » Sat Feb 25, 2023 7:50 pm

KenLowe wrote: ↑Sat Feb 25, 2023 7:36 pm To get genlock, I now need to increase CLKDIV to around 1278.

You should not need to use the CLKDIV command at all - the default value (now 1279/0x4FF) should work correctly in all circumstances.

(This value has changed because it's now all running at 251MHz, rather than 250MHz)

KenLowe wrote: ↑Sat Feb 25, 2023 7:36 pm However, when I do that, I now see a slight pulsing effect on the Lenovo monitor. I think the characters grows slightly, and then jumps back to the original size, and this repeats about twice a second.

What's it like at the default value (1279)?

KenLowe wrote: ↑Sat Feb 25, 2023 7:36 pm The Dell monitor works fine. There's still no noticeable shimmering or pulsing.

Thats good then.

Dave

KenLowe · Post by **KenLowe** » Sat Feb 25, 2023 8:25 pm

hoglet wrote: ↑Sat Feb 25, 2023 7:50 pm
You should not need to use the CLKDIV command at all - the default value (1279) should work correctly in all circumstances.

(The value has changed because it's now all running at 251MHz, rather than 250MHz).

What's that like at the default value (1279)?

I did wonder about the CLKDIV command. 1279 doesn't make much difference. There's still a definite pulse. Unfortunately it's very difficult to pick it up on video, but you can just about see it on the vertical bar of the letter 'N':

https://youtu.be/oHTVHFLWdtE

BigEd · Post by **BigEd** » Sat Feb 25, 2023 8:31 pm

(pretty visible if I pause the video and single-step with < and >)

hoglet · Post by **hoglet** » Sat Feb 25, 2023 8:56 pm

One of two things is happening here:
- the genlock PLL is not performing as expected, and is occasionally having to apply a large correction which is definitely visible (like this, on my monitors as well)
- the genlock PLL is performing as expected, and is only ever applying small corrections, but these are visible on your monitor as a 1px shift

A large correction changes the pixel clock frequency by ~3/1280 (over the whole frame); a small correction changes it by ~1/1280. I was hoping, given the resolution is VGA (640x480), that a 1/1280 change would not be visible. That's certainly the case on all my monitors. But it completely depends on how the monitor is calculating the sample points.

It would be really useful to get a serial log from the Pico, if you have a way to hook up a cable to GPIO0. That would confirm if you are ever getting large corrections.

It would also be useful to try manually tweaking the Lenova's CLOCK setting, which I expect will have more impact than the PHASE setting. But do play with both. The CLOCK setting will only need a very small change. Then try the full range of PHASE.

Dave

KenLowe · Post by **KenLowe** » Sat Feb 25, 2023 9:40 pm

I'll set up the serial log tomorrow. That'll take a little bit of effort!

I have been tweaking the Lenovo CLOCK and PHASE settings whilst doing these tests, but neither seem to have much effect. The clock defaults to 50% and adjusting it in either direction just seems to cause the screen to shift left or right a little bit, whilst stretching and shrinking the picture very slightly at the same time. The phase does even less. I'll be a bit more scientific about these tests tomorrow and document the results.

KenLowe · Post by **KenLowe** » Sat Feb 25, 2023 9:49 pm

Here's a little break out board for the PL4 VSYNC and HSYNC signals. It's an odd shape so it can clear the power jack and associated case support.

This board is not essential, and would only ever be used if you wanted to get video output directly from the 6847, whilst at the same time getting video output from the PicoVGA.

: PL4 break out board

Edit: I've decided to go with a more minimalist approach. I've ditched the box header, and gone with a simpler pin header. This new 2x05 header sits directly in line with the PL4 connector making it easier to get the ribbon out of the case. It avoids any clashes with the power jack and its case support. If I've got my measurements right, I should be able fit an IDC ribbon connector onto the 2x05 pin header, leaving enough clearance at the edge of the IDC connector to plug in the Dupont connector onto the 2x01 sync header. The 2x01 sync header will sit marginally underneath the Atom heat sink, but I don't think that's really a problem.

: PL4 break out board V2 - 3D Render

: PL4 break out board V2 - PCB

KenLowe · Post by **KenLowe** » Sun Feb 26, 2023 1:57 pm

hoglet wrote: ↑Sat Feb 25, 2023 8:56 pm It would be really useful to get a serial log from the Pico, if you have a way to hook up a cable to GPIO0. That would confirm if you are ever getting large corrections.

Right, here I've powered on the Atom, set up the serial port on my PC, and then set GENLOCK to 1 on the Atom. CLKDIV is at the default setting:

Code: Select all

With this, I still see pulsing on the Lenovo screen, maybe 4 pulses per second. Adjusting the monitor CLOCK setting up or down from the default 50 causes the whole screen to crawl left or right; shrinking and growing slightly as it crawls. It doesn't affect the pulsing. The PHASE setting has no effect at all.

hoglet · Post by **hoglet** » Sun Feb 26, 2023 6:56 pm

Hi Ken,

KenLowe wrote: ↑Sun Feb 26, 2023 1:57 pm With this, I still see pulsing on the Lenovo screen, maybe 4 pulses per second. Adjusting the monitor CLOCK setting up or down from the default 50 causes the whole screen to crawl left or right; shrinking and growing slightly as it crawls. It doesn't affect the pulsing. The PHASE setting has no effect at all.

Thanks for going to the trouble of testing this.

That confirms that the genlock PLL is behaving as I would expect, and is only every applying a correction of one to the clock divider. This results in a 780ppm change in the clock frequency, which is obviously still too much for the HSYNC PLL in your Lenova monitor to deal with.

This 780ppm change comes from the Pico PIO clock divider only having an 8 bit fractional component, and the fact we are normally dividing by 5. i.e. 1000000/5/256 = 780pm. For comparision the Raspberry Pi PLLs (I think) have a 12 bit fractional component, and are running at much higher VCO frequency, So the divider is higher, more like 100 I think. This gives a step size of 1000000/100/4096 = 2.44ppm.

What's needed on the Pico is a way of significantly reducing the step size, and that really doesn't exist.

This afternoon I've been trying one more approach. Keep the pixel clock fixed, but vary the horizontal line length. I'd initially discounted this, because the line is 800 pixels long, so varing it by one pixel would amount to a 1250ppm change. But I've found a way to make the scanvideo timing state machne run at the system clock (250MHz ish) rather than the 2x the pixel clock (50MHz ish). So now the effective line length (h_total) becomes 4000 pixels, and a one pixel change to h_total amounts to a 250ppm change. This is 3x better, but that may still not be enough.

Anyway, I've pushed this change (all done with #ifdefs) as commit bc90c6faf

It's pretty ugly and requires a change to pico-extras to make the timimg_state struct accessible.

I'm fairly sure this won't help, but here's another build to try if you are willing:

bc90c6faf.zip: (31.25 KiB) Downloaded 21 times

I've also got an improved version of Colour Test:

COLTEST.zip: (612 Bytes) Downloaded 19 times

Pressing the shift key will toggle genlock (it will be off initially)

Also, changing line 200 from:

Code: Select all

200 STA #8100,X

to

Code: Select all

200 STA #8100,Y

inverts the bottom half of the test pattern.

That lets you more precisesly see where the palette change is happening:

There is scope, I think, for one more improvement, which would reduce the step size to 125ppm. But that's even more hacky!

Dave

KenLowe · Post by **KenLowe** » Sun Feb 26, 2023 9:08 pm

Thank you for doing all this work!

Firstly, on my Lenovo:

With genlock off, there is a very noticeable shimmer that starts about 6 characters in from the left for about 20 character. Characters at the very start and end of the screen are steady.
With genlock on, the pulsing effect appears again, along with the noticeable shimmer described above.

Secondly, on my Dell:

With genlock off, I am seeing a bit of shimmer at the right hand side of the screen. It starts about 8 characters from the end.
With genlock on, I am seeing the same shimmer at the right hand side of the screen. Again, it starts about 8 characters from the end.

I'm worried that you're putting an awful lot of effort into this, for what might be a very limited number of monitors. I'd be more that happy to accept that I just need to use a different (Dell) monitor!

hoglet · Post by **hoglet** » Sun Feb 26, 2023 10:30 pm

I find do find stuff very interesting to work on, and it's still not clear what the best approach is here given the Pico's limitations.

Also, I can guarantee you won't be the only one with a fussy monitor.

I think the issue you are seeing on both monitors with Genlock off is because with the bc90c6faf build the nominal line length (h_total) is actually more like 799 pixels rather than the 800 pixels the monitor is expecting. Depending on the monitor pressing the auto calibration button might help, or it may need clock and phase adjusting. I just tried this on my Dell and was able to eliminate all of the artifacts by changing the clock setting to -1 then adjusting phase.

Anyway, thanks for the feedback, and the result was not unexpected...

Dave

KenLowe · Post by **KenLowe** » Sun Feb 26, 2023 11:23 pm

hoglet wrote: ↑Sun Feb 26, 2023 10:30 pm I think the issue you are seeing on both monitors with Genlock off is because with the bc90c6faf build the nominal line length (h_total) is actually more like 799 pixels rather than the 800 pixels the monitor is expecting. Depending on the monitor pressing the auto calibration button might help, or it may need clock and phase adjusting. I just tried this on my Dell and was able to eliminate all of the artifacts by changing the clock setting to -1 then adjusting phase.

Ok, so adjusting the phase on my Dell worked for me too.

No such luck on the Lenovo, though.

hoglet · Post by **hoglet** » Sat Mar 04, 2023 1:32 pm

I've done a bit more work on the genlock code:
- refactored the code so the bulk of the genlock implementation is in it's own source file
- defined an common interface for genlock implementations
- updated the GENLOCK N command to allow switching between implementions at run time
- replaced the adhoc control code with a properly designed "PD control" based algorithm

I also wrote a BBC Basic simulation of the PD control, to allow the parameters to be tuned: Owlet link

In BBC Basic, the PD controller is basically these three lines:

Code: Select all

330 P=P+(D%-LD%)*A+D%*B
340 IF P<MINP P=MINP
350 IF P>MAXP P=MAXP

D% is the VSync error (in micro-seconds)
LD% is the VSync error in the previous frame
A and B are constants
P is the parameter being varied

The different genlock implementations (selected by the GENLOCK command) are:
- N=0 is genlock off
- N=1 is genlock on, by varying CLKDIV (780ppm step size)
- N=2 is genlock on, by variying HTOTAL (125ppm step size)
- N=3 is genlock on, by varying VTOTAL (1900ppm step size)

Here's a simulation of the N=2 mode:

This maintains the VSync offset to within +/- 4us

Ken, it's possibly worth you retesting the N=2 mode, as the implementation is now a bit better. You may still need to manually tweak CLOCK and PHASE on monitor.

There is also a GENDEBUG <0|1> command that enables/disables debugging to the serial port.

Here's the latest build:

bfb9c28b.zip: (31.89 KiB) Downloaded 18 times

And here's an updated COLTEST program which uses the 0,1,2 and 3 keys to change between modes:

COLTEST.zip: (663 Bytes) Downloaded 19 times

There is not much more that I can think of doing on this now.

Dave

stardot.org.uk

Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom

Re: Combined VGA / Tube interface board for Atom