6502 Beeb instruction timing tester

[dp11]

I've knocked up a quick test program to check the timing of the 6502 instructions to help emulator creators. The emulator requires the user via to be emulated as well.

so far I've only found B-em fails zp,X instructions type instructions.

NB Masters have a 65C02 processor so some of the instructions have slightly different timings which isn't handled yet.

Comments welcome.

EDIT : Now on github : https://github.com/dp111/6502Timing
also slightly improved testing mainly adding RTI test

[dp11]

Improved version now tests undocumented 6502 instructions as well.

This now shows more error B-em and errors in BeebEm

[chrisn]

Thanks! This is a really useful set of test cases.

The test reported errors in BeebEm for instructions 83 (SAX (zp,X)), 8f (SAX abs), b3 (LAX (zp),Y), bb (LAS abs,Y). These are all now fixed.

One thing I noticed is that line 3320 should have &72 rather than &74:

Code: Select all

PROCF(B%,"&B3 LAX (&72),Y")

[dp11]

Well spotted, now fixed in my version. I'm just porting to beebasm so non beeb users can make use of it , then I might to 65C02 as well.

[dp11]

Now on github : https://github.com/dp111/6502Timing
also slightly improved testing mainly adding RTI test , first post updated

[hoglet]

I just tried this on BeebFPGA:

For I while read this as indicatating problems with opcodes 01 and opcode FF.

Then I looked at the code and saw this was just a fixed message.

I think you could make this clearer for first time users:

Code: Select all

6502 instruction timing checking
Only errors are printed
(01=1 Cycle short,FF=1 Cycle long,etc)
Checking documented instructions...
... passed
Checking undocumented instructions...
... passed
Done!

Dave

[BigEd]

Ahem, yes, I mis-read it the same way!

[dp11]

Thanks for the suggestions, I will make the change

[dp11]

I've updated the GitHub version, I've also added the build date. I probably need to adjust the welcome txt to improve clarity. I've add a CLI test with a warning it might fail, but it's always passed for me. BRK is the last instruction that has no forum of test as I think it is too difficult to get an accurate result.

[dp11]

Github updated with new tests for 65C12 instructions. Now there are two ssd files one for 6502 ( beeb) and one for (65C12) master .

A few more emulators appear to have issues with the master instructions. Its late so I'll list the details later.

[scarybeasts]

Github updated with new tests for 65C12 instructions. Now there are two ssd files one for 6502 ( beeb) and one for (65C12) master .

A few more emulators appear to have issues with the master instructions. Its late so I'll list the details later.

Nice tests. beebjit exits for both processor types because of unimplemented opcodes and my laziness.
For the master case, beebjit exits here, which reminds me of an unsolved mystery:

case 0x5C: /* NOP abx */ /* Undocumented. */ /* NOP abs (8) */

... the weird 8 cycle NOP! We know it takes 8 cycles in the normal case, but I don't think anyone looked at what read/write addresses it might put on to the bus on which cycles.
For example, if we engaged a bit of cycle stretching with 0x5C 0x00 0xFE -- NOP $FE00, for how many ticks does it slow down by hitting cycle stretching for the 1MHz access?


Cheers
Chris

[dp11]

I wasn't looking at 1MHz slow down with this. Adjusting the source source should give an easy way to tell on a real machine how long it takes. That is something I can look at. It then would need a logic analyser to find out the actual timing. Maybe hoglets decoder stuff might help here.

Beebjit also fails some BCD timing tests on a master. I've actually been using beebjit during development of this with tests on real machines and jsbeeb when things didn't quite matchup with various sources of documentation. Nb there are a lot of subtle errors on the internet:)

[Rich Talbot-Watkins]

... the weird 8 cycle NOP! We know it takes 8 cycles in the normal case, but I don't think anyone looked at what read/write addresses it might put on to the bus on which cycles.
For example, if we engaged a bit of cycle stretching with 0x5C 0x00 0xFE -- NOP $FE00, for how many ticks does it slow down by hitting cycle stretching for the 1MHz access?

It actually has been documented!

Finally, op-code 5C consumes 3 bytes and 8 cycles but conforms to no known address mode; it remains interesting but useless. I tested the instruction "5C 1234h" (stored little-endian as 5Ch 34h 12h) as an example, and observed the following: 3 cycles fetching the instruction, 1 cycle reading FF34, then 4 cycles reading FFFF.

So looks like cycle stretching would never occur!

[chrisn]

Github updated with new tests for 65C12 instructions. Now there are two ssd files one for 6502 ( beeb) and one for (65C12) master .

A few more emulators appear to have issues with the master instructions. Its late so I'll list the details later.

I've just fixed the various issues this identified in BeebEm's Master emulation. I notice you also have code to test the 65C02 in the second processor. Is that ready to try out? I suspect BeebEm will have lots more errors there...

[dp11]

I've just fixed the various issues this identified in BeebEm's Master emulation. I notice you also have code to test the 65C02 in the second processor. Is that ready to try out? I suspect BeebEm will have lots more errors there...

65C02 is at an early stage, I'm just trying to build a roughly generic test 65xx timing test suite as I know people have been putting 65C02 into the beebs. This test suite may via some configuration spit out timing code for other platforms too.

I'm not yet sure how to time the instructions on the Copro as there isn't a timer available.

[hoglet]

Github updated with new tests for 65C12 instructions. Now there are two ssd files one for 6502 ( beeb) and one for (65C12) master .

A few more emulators appear to have issues with the master instructions. Its late so I'll list the details later.

I was hoping you would do a 65C12 version, as the cycle accuracy of the 65C12 core (from AlanD) in BeebFPGA has never been comprehensively tested. The original core never claimed to be cycle accurate, but it's quite close, and I've been fixing issues as they are identified.

And this test has shown a few remaining issues:

I'm not surprised at the decimal mode issues, as I haven't paid much attention to that mode.

The NOPs should be easy to fix.

I need to dig into:
- ASL/LSR/ROL/ROR addeFE,X
- RTI

These should all take 6 cycles, and the FF error means they are actually taking 7 cycles, correct?

Looking at the CPU implementation, I can see that looks very likely.

Dave

[hoglet]

This is the 65C12 Master in a freshly compiled b-em:

[tom_seddon]

I'm not yet sure how to time the instructions on the Copro as there isn't a timer available.

You can simply run a lot of iterations, and test using TIME. My NOPs timing test does this: https://gist.github.com/tom-seddon/b974 ... 7fa9355e0d (for output, see https://github.com/mattgodbolt/jsbeeb/i ... -505599722). It runs each NOP 655,360 times, which is enough to run correctly on a 4 MHz 65c02 without taking excessively long on the 2 MHz Master. Run enough iterations and any noise from IRQs and so on doesn't matter.

If doing this properly, probably better to auto-detect the number of iterations required. It'd be nice to accommodate everything from the Electron to the pi copro in 250+ MHz mode.

--Tom

[dp11]

@ Tom , that a good idea, I'm doing similar in my new version of CLOCKSP. I've thought of a way of reasonable easily doing this. More things to test

[dp11]

These should all take 6 cycles, and the FF error means they are actually taking 7 cycles, correct?

Thats right .

[dp11]

Does anyone have any preference to which comes next ? 65C02 co processor or 1MHz clock stretching testing?

The b2 emulator has some errors. I haven't tested Mame yet. jsbeeb appears to be good.

Also I think is should be easy to make it build a C64 test suite, but I know nothing about C64. There are other 6502 emulator platforms that with a small effort of adding the 6522 timer via register to the emulator, could be tested e.g. Lib6502 and py6502 etc.

PS I've been check against my hardware and slightly shocked the the CLI test has never failed.

[chrisn]

Does anyone have any preference to which comes next ? 65C02 co processor or 1MHz clock stretching testing?

I think both are useful, but would suggest 1MHz clock stretching first.

[dp11]

Does anyone have any preference to which comes next ? 65C02 co processor or 1MHz clock stretching testing?

I think both are useful, but would suggest 1MHz clock stretching first.

Thanks for the nudge. I've finally found a timing difference in jsbeeb! I've got lots more work todo.

[dp11]

New ssds for Master 1MHz and Beeb 1MHz clock stretching test added. I've check this against real hardware, but before you adjust any emulators please check that the adjustments are sensible, I could have subtle errors.

PS It would be good to have a few other real hardware tests done on these ssds just to confirm the results are stable.

[dp11]

The 1MHz bus slow down tests have shown timing difference between real hardware every emulator I have tried.

[scarybeasts]

It actually has been documented!

Oh nicely found! As of latest GitHub master, 8-cycle NOP is implemented I think that was the last 65c12 gap.


Cheers
Chris

[scarybeasts]

Beebjit also fails some BCD timing tests on a master. I've actually been using beebjit during development of this with tests on real machines and jsbeeb when things didn't quite matchup with various sources of documentation. Nb there are a lot of subtle errors on the internet:)

beebjit is now clean for Master / 65c12 as of GibHub latest master.
I wasn't accounting for BCD cycles in the new 65c12 addressing mode "id".
And there was a terrible, terrible embarrassment for the 65c12 BCD modes "abx" and "aby" -- the incorrect address was being referenced, leading to not only timing errors but also awfully incorrect results. Thanks for helping me catch that.


Cheers
Chris

[chrisn]

PS It would be good to have a few other real hardware tests done on these ssds just to confirm the results are stable.

On my model B, 6502timing1M reports

Code: Select all

Checking undocumented instructions...
&9E SHX (A11, SXA, XAS) addrFF,Y  02
&9C SHY (A11, SXA, XAS) addrFF,X  02

[dp11]

Interesting if we have unstable results I'll add a note to the instruction.

[TobyLobster]

On my model B, 6502timing1M reports

Code: Select all

Checking undocumented instructions...
&9E SHX (A11, SXA, XAS) addrFF,Y  02
&9C SHY (A11, SXA, XAS) addrFF,X  02

I get the same here on a real BBC Micro. This 6502A chip: https://tobylobster.github.io/mos/6502a.png