Benchmarks

[baz4096]

MicroDigital Omega, RISC OS 4.03

302MHz StrongARM SA110 rev T, 128MB RAM 133MHz FPE 4.09

Results:
Dhrystone/sec: 551318.4
Whetstone/sec: 3709.012
Main memory read MB/s: 108.0
Main memory write MB/s: 125.3
CLOCKSP: 4392.87MHz
Mandelbrot: 22.82s
Reach - Galaxy: 117
Reach - Tunnel: 555

[SarahWalker]

Added results for ARM710 (vs ARM710a). Memory read bandwidth is noticeably higher than ARM710a, but the higher latency on cache fills means every other test runs slower.

An additional discovery digging through the RO 3.71 boot code is that when an original 710 is present, ROM burst mode is disabled (which cuts ROM speed by about 1/3). This would explain the outsize difference on the BASIC and FP heavy benchmarks between the 710 and 710a.

[sirbod]

An additional discovery digging through the RO 3.71 boot code is that when an original 710 is present, ROM burst mode is disabled (which cuts ROM speed by about 1/3). This would explain the outsize difference on the BASIC and FP heavy benchmarks between the 710 and 710a.

Slightly off topic, but could you let me know the CPUID of your 710 and 710a. I'm guessing the 710 is 41007100 and the 710a is higher?

The ARM7 macrocell used in the ARM700/710/7500 has some rather odd quirks in general, for example there's this erratum that doesn't appear on any other ARM. As far as I know errata were not published for the ARM7 macrocell based CPU, so it's possible Acorn were implementing a workaround for a known errata by disabling ROM burst mode?

[SarahWalker]

Slightly off topic, but could you let me know the CPUID of your 710 and 710a. I'm guessing the 710 is 41007100 and the 710a is higher?

710 = 0x41007100
710a = 0x41047100

The ARM7 macrocell used in the ARM700/710/7500 has some rather odd quirks in general, for example there's this erratum that doesn't appear on any other ARM. As far as I know errata were not published for the ARM7 macrocell based CPU, so it's possible Acorn were implementing a workaround for a known errata by disabling ROM burst mode?

My best guess was that IOMD & the nibble mode ROM didn't work correctly with the longer (8 word) read bursts 710 performs due to the longer cache lines. The StrongARM card may be working around this by breaking up cache line fills into 2 4 word bursts (ie forcing an N cycle in the middle of the burst). That is just speculation though.

[SarahWalker]

Thanks to IanJeffray I now have a MEMC1 (+PAL) and have been able to benchmark the earliest (and slowest) Arc configuration. Acorn claimed a 10% improvement for MEMC1a, how accurate was that?

Interestingly it looks like they _understated_ it. 15% improvement on average (though Galaxy as an outlier shows how much impact the faster multiply instructions can have).

[IanJeffray]

Interestingly it looks like they _understated_ it.

Haha. That's cool!
I wonder if you'd be able to measure any impact of ARM2 vs ARM3 or even RISCOS2 vs RISCOS3 with MEMC1 vs MEMC1A. I'd noted that the 64MHz A7000+++ benchmark initially appeared worse than a 56MHz Mico, but showed that the RISC OS version did make a massive impact to skew the benchmarks - I've no idea whether suchlike could make a difference here (I expect not) but it may be more to add to the mix/understanding.