Shimmering Teletext on BBC/Master

[maniacminer]

I had some free time over the holiday period to think some more about the problems I have been having with MODE7 (Teletext) and various add-ons (VideoNULA / BBC2DVI) I went through the entire clock circuit from top to bottom, replacing everything in the path and that made a huge improvement, but it still had that occasional shimmer and the TV, being far higher resolution than the BBC can display, assumes that shimmer is useful information and displays it next to where the "real" image should be.

So I decided to bite the bullet and replace the crappy 6MHz clock generation circuit with my own. I have a big box of 74F DIL logic from getting Transputer stuff working again, so I decided that would be the basis for the circuit. I then worked out from the SAA5050 datasheet that there couldn't be much error between the 1MHz register clock and the 6MHz pixel clock. Some simple maths and the only frequency that fits both 6 and 8 is 48.

What I did was to use a 48MHz clock generator module, use three flip-flops to divide the signal from 48MHz to 6MHz then use a divide by three circuit using another three flip-flops and some assorted logic (implemented with NANDs) to give me the 16MHz base clock. I then disconnected the on-board clock by bending up the output pin of the clock inverter (IC43 pin 2) and that stopped the signal going to the jumpers at LK60. I then connected the 16MHz from my board to LK60. I then lifted pin 19 of IC32 (SAA5050) and connected that instead to the 6MHz output from my board.

I took a video of the 'scope for the original 6MHz clock

BBC 6MHz clock.mp4

(3.6 MiB) Downloaded 37 times

and then my 6MHz clock

My 6MHz clock.mp4

(3.61 MiB) Downloaded 35 times

The result in a pin-sharp, totally steady MODE7

The only issue was I named the pins in reverse from not noticing the pin numbers were backwards in the KiCad model I was using

Board in place

No noise!

[SimonSideburns]

I love that sharp image of Mode 7. I don't think I've ever seen one so clear and precise.

[maniacminer]

I love that sharp image of Mode 7. I don't think I've ever seen one so clear and precise.

Yup it looks lovely and smooth, no distortion or wiggles.

[maniacminer]

I have mounted another PCB into the Beeb, slightly more involved, but it works very nicely. It takes me about an hour to fit as a couple of ICs need removing and sockets installed, plus I use the power present on the serial port "overclock" jumper that is a hard-wired link (S28)

I took a before and after photo of asterisks, as they easily show up the malformation of characters on this screen (Sony KDL-46X4500) and shows my original problem with the VideoNuLA board in MODE7.

Board mounted in the Beeb on top of the UHF modulator

Without the clock mod board fitted

With the clock mod board fitted

VideoNuLA problem.mp4

The problem I was having with the VideoNuLA in MODE7

(4.04 MiB) Downloaded 102 times

A minor mechanical incompatibility with the IFEL RAM/ROM board :P

[lurkio]

Please forgive my utter ignorance of all things hardware, but is this a mod that can be done to a standard unexpanded Beeb (and, if so, would it help?), or is it only suitable for Beebs with the VideoNULA installed?

[Deleted User 9295]

is this a mod that can be done to a standard unexpanded Beeb (and, if so, would it help?)

The circuit that Acorn devised for deriving a 6 MHz clock from a 16 MHz clock (which initially I wasn't convinced was even possible without starting at a higher frequency!) inevitably gives rise to an output with lots of phase modulation, and that directly affects the quality of the MODE 7 characters. Whether that really matters depends on your sensitivity to the defects; I can't say I've ever found the legibility to be significantly impaired so personally I wouldn't feel the complexity of the mod is justified.

But if you're dissatisfied with the quality of MODE 7 I assume the mod is equally applicable to an unexpanded Beeb, although the OP will no doubt confirm.

[maniacminer]

Please forgive my utter ignorance of all things hardware, but is this a mod that can be done to a standard unexpanded Beeb (and, if so, would it help?), or is it only suitable for Beebs with the VideoNULA installed?

I am using an un-expanded Master and Beeb to drive my TV. I couldn't use the VideoNuLA because of the problems I was having with MODE7. So I made the board and noticed the difference when driving the TV. I guess I didn't really notice until I could switch between the Acorn 6MHz-ish circuit and mine. It just gives a very smooth, as Mullard intended, Teletext display. My next steps are to get another VideoNuLA and also Hoglet's Pi RGB->HDMI and be able to use them without any of the graphical glitches.

[maniacminer]

is this a mod that can be done to a standard unexpanded Beeb (and, if so, would it help?)

The circuit that Acorn devised for deriving a 6 MHz clock from a 16 MHz clock (which initially I wasn't convinced was even possible without starting at a higher frequency!) inevitably gives rise to an output with lots of phase modulation, and that directly affects the quality of the MODE 7 characters. Whether that really matters depends on your sensitivity to the defects; I can't say I've ever found the legibility to be significantly impaired so personally I wouldn't feel the complexity of the mod is justified.

But if you're dissatisfied with the quality of MODE 7 I assume the mod is equally applicable to an unexpanded Beeb, although the OP will no doubt confirm.

Yes, I did look at the schematic many years ago (30+) to figure out why I couldn't genlock onto a Beeb MODE7 using the same SAA5050 that worked externally. The penny dropped rather quickly when looking for the source of "TR6" on IC5, traced it back and saw the flip-flop/capacitor/XOR glitch-switch and then realised it would be a lot more work. I do recall trying to make my own PLL to run off the 1MHz clock to try and keep the sync between the system clock and the 6MHz clock, they have to be very close or the chip goes wild, that didn't work all the time and always died when I wasn't looking at it I ended up driving it from the 1MHz bus with 1kB of local SRAM and a sync separator, it was happy then

The circuit does work for an unexpanded BBC/Master. It is only once you've seen the difference that you'll notice it, as the old saying goes, if you've never had it, you'll never miss it To quote a mostly-reliable source Wikipedia - " This gave a particularly stable and flicker-free arrangement on interlaced displays." https://en.wikipedia.org/wiki/Mullard_SAA5050

[maniacminer]

The 16MHz from 48MHz is a divide by 3, I've had a few people ask me how it is done because I am told "it is impossible" - like my old C.S. teacher who said a four NAND -> XOR gate is impossible, I still remember his face when he checked the truth table - damn, I should have made a t-shirt of that schematic

[Gelpack]

If you examine the 16Mhz oscillator on the board using a Spectrum Analyser, the centre frequency is actually 48MHZ.

They should have done what you did in the first place, and then maybe we all would not have had to put up with these problems.

Well done !

[maniacminer]

I think Acorn had enough problems with RFI as it was Your spectrum analyser should show a 16MHz centroid with harmonics? Amusingly, the RFI from the 2MHzE and 1MHzE creates whine in the built in audio amplifier, a bit like an old AM radio having IF drift. I really hate the audio circuitry on the Beeb, it's so dirty, I'm going to do a board for that one day, a plug-in for the 76489 and bypass all the audio circuitry, I just need to finish my "prototyping" Beeb (an issue 3 with multitudes more issues...) so I can add and remove components on the fly. Maybe even try producing sine waves with some wave shaping and dropping the 76489 clock to 3MHz to get some decent bass and a decent power amplifier

[Gelpack]

I think Acorn had enough problems with RFI as it was Your spectrum analyser should show a 16MHz centroid with harmonics? Amusingly, the RFI from the 2MHzE and 1MHzE creates whine in the built in audio amplifier, a bit like an old AM radio having IF drift. I really hate the audio circuitry on the Beeb, it's so dirty, I'm going to do a board for that one day, a plug-in for the 76489 and bypass all the audio circuitry, I just need to finish my "prototyping" Beeb (an issue 3 with multitudes more issues...) so I can add and remove components on the fly. Maybe even try producing sine waves with some wave shaping and dropping the 76489 clock to 3MHz to get some decent bass and a decent power amplifier

That's what I expected, but Nope, the SA, definitely shows the centre as 48Mhz 16mhz as a harmonic. Its a weird one, someone did explain why and its in one of my posts but I cant remember which one, if I find it I will post it.

[KenLowe]

I have mounted another PCB into the Beeb, slightly more involved, but it works very nicely. It takes me about an hour to fit as a couple of ICs need removing and sockets installed, plus I use the power present on the serial port "overclock" jumper that is a hard-wired link (S28)

I've got a model b that gives me a rather wonky mode 7 once it's warmed up. I previously replaced the crystal but it didn't make any difference, so thought I might try a circuit similar to this to see if it improves things. On inspection of the photo of the circuit you've built I notice that you still seem to be using the original 16MHz circuit for something.

I understand that you've taken the new 16MHz signal from your board and wired it back into the beeb motherboard by lifting IC40 pin 11, and then connecting your new 16MHz signal into the beeb motherboard in place of IC40 pin 11. That bit seems to make sense.

But what I'm less clear on is that it looks like the lifted ('redundant') leg of IC43 pin 11 has been wired back into something else. Can you clarify what you've done there? Edit: Ah. Maybe you've just insulated the leg to prevent any short circuits???

Also, I notice on your divide by 3 schematic that you've specified 74F parts. Is that essential, or would standard 74LS or 74HCT parts also be suitable? I notice that the original divider circuit on the beeb motherboard is made up of 74LS parts, so I'm assuming it's not that critical.

[arg]

Also, I notice on your divide by 3 schematic that you've specified 74F parts. Is that essential, or would standard 74LS or 74HCT parts also be suitable? I notice that the original divider circuit on the beeb motherboard is made up of 74LS parts, so I'm assuming it's not that critical.

The original design factored in the slowness of 74LS as part of the design - it was more about analogue delays than digital logic.

This divide down from 48MHz on the other hand will give perfect results with infinitely fast parts and will fail if they are too slow: the feedback loop top left must propagate within a single cycle of 48MHz (20.8ns) and meet the setup of the D-type input or else it fails totally, while the output stage risks asymmetry in the resulting 16MHz if the delays are significant (I must admit I don't quite understand one of the choices in the design as drawn: I would have thought that using Qbar on U3A and thus getting rid of U4A would have matched the delays more closely, though I haven't drawn out a timing diagram to prove this, and maybe the ULA doesn't care anyhow).

At 48MHz, 74LS or 74HC are out of the question as too slow. If building it in modern parts, I'd be tempted to do it all at 3V and use single-gate packages so you can have the gate you want rather than constructing other functions out of NAND gates; many of the modern families would do, like 74AUP or 74LVC, but 74LV or 74LCX/LVX are too slow.

Either way, the whole thing is fast enough and critical enough that any deviation from a known good solution needs you to sit down and do some calculations first.

[KenLowe]

Thanks for the feedback. For the 16MHz clock / divide by 3 circuit I was considering implementing this circuit which uses fewer gates:

https://pages.mtu.edu/~suits/electronic ... rcuit.html

I was thinking about using single gate 74LVCxGxx series, and it's worth noting that these do also work at 5v, so everything can still be powered from the 5v rail.

For the 6MHz clock / divide by 8 circuit, I was just going to use three single gate flip flops (like the 74LVCxG74). I might try knocking something up to see if it works.

[arg]

For the 16MHz clock / divide by 3 circuit I was considering implementing this circuit which uses fewer gates:

It's not really fewer gates if you have the right functions: this thing is 3 flipflops and 4 NOR gates, while the other one was four flipflops, one AND, one OR and an inverter - so 7 functions either way.

You might possibly manage to get a win out of the universal gates (1G57/97/98) - which are worth considering anyhow to simplify your BoM, and might possibly sweep up the three NOR gates bottom right of that circuit into one device if you can find the right one. Note also that you'd prefer to be using only Q here rather than Q plus Qbar so that you can go for the smaller 1G79/80 that have only one or the other.

I might try knocking something up to see if it works.

Better to do the work on paper so you don't build one in winter that works and then build a batch of them that all fail in the summer...

If you are going for 74LVC1G74 at 5V, then there's a propagation delay of 4.1max and setup of 1.1ns total 5.2ns so you've got 20.8-5.2 = 15.6ns for the gates in the feedback loop. That's plenty for a single gate (74LVC1G97 for example, 6.1ns max at 5V), but getting tighter if you stack multiple gates to build a different function, or if you run at 3V3. Also hold time of 1.0ns, but that's satisfied automatically here by the minimum propagation delay.

[KenLowe]

For the 16MHz clock / divide by 3 circuit I was considering implementing this circuit which uses fewer gates:

It's not really fewer gates if you have the right functions: this thing is 3 flipflops and 4 NOR gates, while the other one was four flipflops, one AND, one OR and an inverter - so 7 functions either way.

Actually only 2 flip flops. And only two different gate types (2 x flip flop & 4 x NOR) to minimise the BoM.

You might possibly manage to get a win out of the universal gates (1G57/97/98) - which are worth considering anyhow to simplify your BoM, and might possibly sweep up the three NOR gates bottom right of that circuit into one device if you can find the right one. Note also that you'd prefer to be using only Q here rather than Q plus Qbar so that you can go for the smaller 1G79/80 that have only one or the other.

I'll have a look at those universal gates. I've never used them before, but they look fairy straight forward to use.

I might try knocking something up to see if it works.

Better to do the work on paper so you don't build one in winter that works and then build a batch of them that all fail in the summer...

If you are going for 74LVC1G74 at 5V, then there's a propagation delay of 4.1max and setup of 1.1ns total 5.2ns so you've got 20.8-5.2 = 15.6ns for the gates in the feedback loop. That's plenty for a single gate (74LVC1G97 for example, 6.1ns max at 5V), but getting tighter if you stack multiple gates to build a different function, or if you run at 3V3. Also hold time of 1.0ns, but that's satisfied automatically here by the minimum propagation delay.

Ok. I obviously need to read the datasheet a bit further. I didn't realise the propagation delay was impacted by the supply voltage.

Thanks for the feedback!

[arg]

Actually only 2 flip flops. And only two different gate types (2 x flip flop & 4 x NOR) to minimise the BoM.

Sorry, yes - 2 flipflops vs 3, not 3 vs 4 as I wrote. But the overall comparison is right. And I was looking to universal gates to minimise the BoM.


Also, I'm a bit concerned the 'simpler' circuit has the possibility to glitch: all three of the signals going into the set of gates that generate the final output are changing at the same time. Probably it's safe if some of the propagation delays are always longer than others (maybe if the inverter at the bottom is always faster than the flip-flop), but I haven't analysed it fully.

Conversely, the circuit with three flip-flops is guaranteed glitch free as the two signals feeding the final combinatorial stage change on opposite phases of the clock. It uses both Q and Qbar on some of the flipflops, but that can be cleaned up just by picking the right logic function for the feedback bit - in fact that part of the circuit (the first two flipflops and the feedback path) are logically identical between the two designs.

[lovebug]

when I saw that divide by 3 was needed the first thing that popped into my head was string 3xflipflop in series and feed the -Q output of the last into the D input of the first . that should work right ?

[arg]

when I saw that divide by 3 was needed the first thing that popped into my head was string 3xflipflop in series and feed the -Q output of the last into the D input of the first . that should work right ?

If you do that, you've got to set the starting condition. These circuits are nearly the same idea - two flipflops, and at any moment only one of: the "D" input; the first Q output; the second Q output, is high. So as with your idea this rotates endlessly and you can take any of those signals to give you a one-pulse-per-3-input-pulses output. Same effect, but the starting condition sorts itself out.

The remaining logic is trying to make the output symmetric. It's not actually clear if that's necessary, given this is feeding the VIDPROC and that maybe uses only rising edges?

The 6MHz does need to be symmetric as the SAA5050 uses both edges of it, but that's easy as it's just a binary divide of the 48MHz.

[lovebug]

ah ! i was only thinking about division , didnt think about the output states

[maniacminer]

Just to clarify, given the number of questions above;

- 74F was selected as I have *lots* of them from repairing/preparing the Transputer exhibit at the TNMoC
- 74F gives very fast, sharp waveforms with little chance of ambiguity - I didn't try other families
- the circuit design with the strange layout was required due to a timing glitch where the cursor would create snow randomly
- the 16MHz clock needs to be fed back into the board, the mod is easily reversible and the socket has the 16MHz flying lead soldered to it, the IC leg is insulated so as not to cause chaos if by some accident, it was to touch the new 16MHz
- I never tried to simplify the design once I had stable signals with the right phase
- I did make a more complicated version that reset the external flip-flops with the system VIA reset and clocking the video ULA flip-flops (can't use reset as the video ULA doesn't have it) until they were all zero - this removed the need to calibrate the display with the RGB2HDMI
- my attempt at a replacement basic video ULA hasn't got far, there's quite a bit in it, but the various clocks are done, so the Beeb will start up and run head-less - lets me do some more thorough testing on the Beebs that eat video ULAs for breakfast!

[KenLowe]

I thought it was time to get my version of this board finished. I decided to keep it simple in the end. I'm only using two different LVC parts; the 74LVC1G02 (NOR) and 74LVC1G79 (d type). These can both be powered from either 5v or 3v3, and I'm planning just to use 5v unless there's a good reason to switch to 3v3, and both are available from JLC in SOT-353 / SC70-5 package with quite fast (<5nS) propagation.

Nearly everything's routed on the top layer, although there are a couple of tracks on the bottom layer.

I'll possibly make a couple of small breakout boards, so I can patch the 6MHz and 16Mhz signals into the mainboard. One of these would sit at IC37, driving into socket pin 8, and the other at IC40 driving into socket pin 11.

Here's the schematic, layout & 3D render:

Schematic

Layout

3D Render

One question I do have... Is the phase of the 6 MHz clock relative to the phase of the 16Mhz clock at all important?

Comments welcome, ahead of me placing an order for a small batch.

[vexorg]

I was looking at my saa5050 recently as it's not working. The 6MHz is a bit nasty, though it's a weird mix of the 2, 4, and 8MHz, meaning the pulse width is different every second waveform. The rounded sine waveof the RC circuit means it depends on the chip threshold rather than a square wave.

[KenLowe]

This is what I'm thinking of doing at IC40 (& similar at IC37). So, you can either jumper J2 and the original clock will be used, or you remove the jumper and attach the external clock to pin 1. I'm planning to use a 74HCT04 for IC37 and a 74ACT00 (both in TSSOP package). I'm hoping the ACT will be fast enough (although, I probably won't be using it, because I'll be using the external clock). I notice that some LVC brands (diodes.com) are 5v tolerant, so I might even try that - although JLC don't have those in stock, so I'd need to solder those on myself:

Schematic

3D render - front

3D render - rear

[vexorg]

Does the 6MHz need to be synchronous with the 1MHz, or can it be free running?

[maniacminer]

Does the 6MHz need to be synchronous with the 1MHz, or can it be free running?

It needs to be synchronous as the SAA5050 has some timing constraints between the 1MHz and 6MHz clocks.

Excerpt from SAA5050 datasheet

https://vd-view.azurewebsites.net/Documents/SAA5050.pdf

[KenLowe]

Does the 6MHz need to be synchronous with the 1MHz, or can it be free running?

Well, the 1MHz will be derived from the same 48MHz clock as the 6MHz clock, so they will always be in sync. But I'm not sure how important the phase shift between the two will be?

Edit, ok so I see @maniacminer has answered that question! And here's the figures to go along with the timing diagram that I'm going to need to comply with:

SAA5050 clock timing requirements

[vexorg]

Was just a thought, if the 6MHz could be free running then a cheap crystal oscillator could have been used. Wasn't sure if it was independent for the pixel clock or needed for data too.

[Super_7b]

Does the 6MHz need to be synchronous with the 1MHz, or can it be free running?

Well, the 1MHz will be derived from the same 48MHz clock as the 6MHz clock, so they will always be in sync. But I'm not sure how important the phase shift between the two will be?

Edit, ok so I see @maniacminer has answered that question! And here's the figures to go along with the timing diagram that I'm going to need to comply with:

BeebClockUpgrade07.JPG

Hi Ken,

Will you be going ahead with this project?

Reading your last few posts, I understand it that there would be a new external clock board to generate the 16MHz and 6Mhz clocks and a couple of "plug-in" boards to fit in sockets replacing ICs 37 & 40 with the option to link in either the original clock or the external clock.

If I have this right, I would certainly be interested in purchasing a set of the 3 boards. You mentioned using 5V tolerant chips, which would be a real plus.

Thanks

Mick