Blitz - Originally known, by the designer, as "Arcin32" - The 32Bit IDE Interface - NOW WORKING!

[daveejhitchins]

I've received some absolutely brilliant news from my ex-partner Dave Prosser.

Schematics, ABEL file and JED file along with a brief description, as far as he can remember, of how it works . . .

And, drum-roll - the number made, just 350 . . .

More importantly - permission to publish ALL the details

More later - Dave H

[danielj]

Awesome news Dave

[paulv]

Yay

Paul

[mr-macrisc]

Nice

[daveejhitchins]

Here's an edited copy of the reply from Dave Prosser:

The interface that APDL called Blitz was internally called “Arcin32”. This uses a Xilinx XC95144 Edit[XC95144XL TQ144 10ns PN: XC95144XL-10TQ144C], which strictly, is still a CPLD not an FPGA, with (IIRC) 144 macrocells and 117 I/O pins Edit[Correct]. This has on-chip flash to hold the programming image data, so is operational immediately at power-up – and yes, it would have been locked, being quite unique in the Acorn market, I didn’t want the design being pinched! This was the only IDE interface using the 32bit data bus width into the Acorn (the drive interface, of course, was only ever 16 bit), but it saved a lot of CPU time converting multiple 16 bit reads into 32bit words, or vice versa on write, so it achieved considerably higher data transfer rates (60%-80%+ ?? compared with the 16 bit interfaces, not sure, can’t remember), when paired with the (then) newer/faster hard-drives. What the CPLD does (in 32bit mode) was to trigger two reads from the hard-drive, and then to merge them to make 1 x 32bit word to return to the CPU. I have a feeling, not sure, that each read request from the CPU worked as a trigger, so it would start the process to get the next two words, while returning immediately the previous 32bit result - not sure, could be wrong about that. The write was easier in that sense, CPU just makes a 32 bit write into the local register, which is then passed on in two parts of 16bit to the hard-drive. There was also some support for the half-baked imitation DMA transfer mode that Acorn supported on the bus.

The FPGA/CPLD script (text file) is an Abel file “arcin32.abl”, which compiled to a .jed (JEDEC) file, as usual. Abel was “Advanced Boolean Expression Language”, which is very similar in concept, syntax and capability to CUPL and PALASM, but nothing like as good as VHDL. Apparently, Xilinx bought this in about 1998 and used this until they had proper VHDL/Verilog support.

The attached files are the latest and final version (release 4 of the CPLD; 2nd release of the pcb – I had 100 made in the first batch and 250 in the second, not sure that all the 2nd got sold in the end, but certainly more than enough to cover the increase in the total purchase cost). You have my permission to publish these files.

Schematics:

ARCIN_32a_Schematic.pdf

(49.12 KiB) Downloaded 159 times

XC95144 TQ144 10C.pdf

(204.95 KiB) Downloaded 161 times

I'll publish the ABEL files when I have a prototype working.

Dave H

[richardtoohey]

(First two paragraphs are repeated as para 1 para 2 and then para 1 para 2 again. Not that it really matters?)

[daveejhitchins]

(First two paragraphs are repeated as para 1 para 2 and then para 1 para 2 again. Not that it really matters?)

Thanks, Richard . . . I shouldn't be editing at 4 in the morning!

Dave H

[daveejhitchins]

I've been checking the schematic nets against the ABEL file I have and noted a few minor differences!

Is there anyone familiar with ABEL that has time to assist with this project? I'd like to ensure that the current ABEL file compiles and produces a .jed file that matches the one I have. I'd also like to understand the differences I'm seeing!

I'm also in the process of putting together a schematic and board layout, in Altum, for a production run. I plan to have 5 x PCB as the current layout and schematic together with 5 x PCB using a revised schematic and layout - I can see some improvements in layout to reduce some of the back-of-board traces. This will just involve some pin reallocations.

Thanks - Dave H

[danielj]

Pop me down as an interested party, Dave (I've also got xilinx programming kit and a riscpc )

[daveejhitchins]

Pop me down as an interested party, Dave (I've also got xilinx programming kit and a riscpc )

Thanks, Daniel . . . Mail sent

Dave H

[danielj]

Thanks, Daniel . . . Mail sent

None received

[daveejhitchins]

Update:

Dave H

ArcIN32C 05-03-19 - Schematic.PDF

(726.62 KiB) Downloaded 137 times

[daveejhitchins]

Update . . . Final (?)

Dave H

ArcIN32C 11-03-19 - Schematic.PDF

(773.56 KiB) Downloaded 124 times

[JonC]

Are you putting the spade power connector on this Dave so it doesn't need a backplane?

[IanS]

Are you putting the spade power connector on this Dave so it doesn't need a backplane?

It's a RISC PC/A7000 only device, it would need a whole different connector (card edge) to work without a backplane.

[JonC]

Are you putting the spade power connector on this Dave so it doesn't need a backplane?

It's a RISC PC/A7000 only device, it would need a whole different connector (card edge) to work without a backplane.

Of course it is! Must have killed too many grey cells over the weeked.

[mr-macrisc]

I always assumed rpc/a7000 but seen a few say worked on other systems too but obv not at 32bit. Not sure if thats true due to way they work but not impossible to belive.

[IanS]

Yeah, I guess it could fall back to 16-bit on a non-RISC PC. Does anyone know for sure if it does? I wonder how it handles being plugged into an Arc with the co-proccessr connections in the middle row of pins.

[danielj]

Well... One place would have told us quite quickly, but for some reason it's been excluded from the internet archive...

Very helpful.

[RobC]

Yeah, I guess it could fall back to 16-bit on a non-RISC PC. Does anyone know for sure if it does?

This would imply that it only works on a RiscPC or A7000:

Unlike earlier ideA interface you cannot fit the Blitz to older machines like the A5000, A400, A540, etc. It can only be fitted to a 'new architecture' machine like a Risc PC. Even if we made it possible to use the Blitz on older machines it would have no performance advantage over the standard ARCIN interface which is less than half the price...

[danielj]

This would imply that it only works on a RiscPC or A7000:

Good digging!

d.

[mr-macrisc]

Always good to have confirmed

[daveejhitchins]

I've not read the whole of the above linked document, as yet.

ideA is a trademark of APDL All other trademarks are acknowledged.

Unless APDL purchased/agreed the right to use ideA from Ian Copestake then the above statement is suspect!

I'll read the rest in the morning . . .

Here's a snippet from DaveP:

I have no idea what changes, if any, that APDL made to the IDE system. I gave Dave Holden a copy of the IDE source code, and permission to make changes to that source code for support purposes, and to apply his own branding for sales purposes. However, I did not give or sell him any rights in the copyright to the original designs. I don't think I gave him any manufacturing details for the hardware.

Similarly, MicroDigital had permission to apply their product names and branding to the boards I did for them, but they never owned any rights in the actual pcb or software designs, apart from an agreement not to sell equivalents in competition. Of course, MicroDigital Ltd are now struck off, if not actually formally liquidated. If anyone should happen to pop 'out of the woodwork' and try to complain about anything, you could just remind them that MicroDigital Ltd owes money for unpaid bills, without which key contracts were never fulfilled.

As BE was never a listed company, and so never liquidated, *we* still own all the copyrights in everything we did - and all our bills were paid (unless legitimately disputed).

On another matter: Daniel is looking into the ABEL code and has noticed that nPS (nPoduleSelect) is listed as a net connected to the CPLD, however, isn't used anywhere within the ABEL coding. Not sure if this indicates that there may be a problem with this code? Anyone any ideas?

Dave H

[IanS]

On another matter: Daniel is looking into the ABEL code and has noticed that nPS (nPoduleSelect) is listed as a net connected to the CPLD, however, isn't used anywhere within the ABEL coding. Not sure if this indicates that there may be a problem with this code? Anyone any ideas?

I think that just confirms it's RISC PC/A7000 only. It will be using the EAS (Easi Space Strobe) which only existed on the later machines.

[daveejhitchins]

I think that just confirms it's RISC PC/A7000 only. It will be using the EAS (Easi Space Strobe) which only existed on the later machines.

Thanks, Ian . . . That explains a lot.

After some more checking - some PCBs - A check to see if the board I have actually works - then . . . Hmmm! Discussion at Wakefield, methinks!!

Dave H

[daveejhitchins]

PCBs ordered . . . x 10 for £15.56 from JLC

Dave H

[danielj]

Try not to think too hard about it.

[daveejhitchins]

Finally have a RiscPC working so I've been able to check if the Blitz interface works . . . I does

Started up, it found the CF card interface OK

Not sure why the text is over the icon?

And this is the start of the Prototype build

Dave H

[mr-macrisc]

Finally have a RiscPC working so I've been able to check if the Blitz interface works . . . I does

Started up, it found the CF card interface OK
IMG_3247.jpgIMG_3248.jpg

And this is the start of the Prototype build
IMG_3249.jpg


Dave H

Knew it would be in good order

[daveejhitchins]

Knew it would be in good order

Building two prototypes at the moment - it's really difficult to do anything anymore - with all finger, arms, legs and toes crossed

If it all works then there'll be a loud noise on the Forum - if it doesn't work there'll be an equally loud silence

Dave H