Required spec for Electron 4164 DRAM? 150ns?

[slikvik55]

As per the title, if I wanted to order some replacements what do I need to be aware of?
Do they need to be 150ns or faster?
Any brand will do?

I understand I could also use 4864?

[danielj]

4164-15 is what I've always used.

d.

[daveejhitchins]

As per the title, if I wanted to order some replacements what do I need to be aware of?
Do they need to be 150ns or faster?
Any brand will do?

I understand I could also use 4864?

PM me . . . I have lots of "pulled" ones I can clean-up, test and send them for the price of P&P.

Dave H.

[1024MAK]

Are you sure that 8146 is not the date code? 8146 would be week 46 in 1981...

Faster DRAM should also work fine. And yes, the brand/make does not matter. However, it is wise checking that the datasheet for the DRAM you are thinking of using does specify that it has page mode access.

64K bit DRAM chips also are either 128 cycle refresh types or 256 cycle types. Acorn used the Texas Instruments TMS4164-15 which are 256 cycle types.

Mark

[mogwaay]

64K bit DRAM chips also are either 128 cycle refresh types or 256 cycle types. Acorn used the Texas Instruments TMS4164-15 which are 256 cycle types.

Mark

Hi Mark, I'm really interested by this 128 / 256 cycle refresh thing as I've implemented a DRAM controller in my 'No-frills' Electron ULA replacement and this is the first I've heard of this and would like to know more. A quick Google on this found another older post of yours:
viewtopic.php?p=290509#p290509
I'm curious how a 64Kb DRAM chip with 8 bit row and 8 bit address would only need a 7 bit, 128 values, strobed to refresh - is it just the lowest order bits in the Rows that are cycled (ie A7 ignored?) or any 128 value?

The Samsung KM4164 data sheet I have which is "128 cycle/2ms refresh" doesnt specify anything about this in it's refresh section.

Doesn't seem to cause an issue, the Elk ULA loops through all 256 rows for generating the Video anyway, so refresh is sorted, I'm just very curious

[1024MAK]

DRAM manufacturers specially designed the 7 bit 128 cycle, 2ms refresh types to maintain compatibility with existing systems that were designed for 4116 DRAM chips. For example, Z80 systems and other MPU systems that had support circuitry with only 7 bit refresh counters.

These DRAM have 7 rows for refresh purposes. The refresh address must be on the A0 to A6 address input pins. Generally the value on A7 is ignored during refresh, so can be logic low or high.

Internally they appear to be comprised of four groups of 64 rows X 256 columns, hence 64K. See the datasheet for the Mitsubishi M5K4164ANP. Or eight groups of 32 rows X 256 columns, see the datasheet for the Motorola MCM6665A.

As the technology of DRAM improved and was further developed, the refresh period was increased to 4ms (256 cycle types). But also other refresh methods became available such as hidden refresh, CAS before RAS, and on chip refresh counter circuitry (meaning there was no longer a need for the system to provide a refresh controller).

Mark

[slikvik55]

PM me . . . I have lots of "pulled" ones I can clean-up, test and send them for the price of P&P.

Dave H.

Hey Dave.

That would be amazing!!! .... but I don't have PM access yet as I haven't posted enough (and yes I meant 4164-15 DRAM )
You may be able to PM me though?

I have two Electrons both showing black and white bars. Could be the ULA and I'm gonna clean the Rev 2 contacts, but I'm pretty sure I'll need to replace the DRAM on at least the Rev 6 board. One of them also has a Slogger Master Ram board fitted, so there's an extra set of DRAM to worry about too!

[daveejhitchins]

PM me . . . I have lots of "pulled" ones I can clean-up, test and send them for the price of P&P.

Dave H.

Hey Dave.

That would be amazing!!! .... but I don't have PM access yet as I haven't posted enough (and yes I meant 4164-15 DRAM )
You may be able to PM me though?

I have two Electrons both showing black and white bars. Could be the ULA and I'm gonna clean the Rev 2 contacts, but I'm pretty sure I'll need to replace the DRAM on at least the Rev 6 board. One of them also has a Slogger Master Ram board fitted, so there's an extra set of DRAM to worry about too!

Check the ULA socket contacts. They fail - to check look at the height of each pin. If broken they sit-low. The Master RAM board doesn't have DRAM! If it isn't soldered-in (?) I'd remove it for testing the Electron.

PM Sent - Dave H.

[slikvik55]

I've just reopened the Iss 6 as I hadn't really checked properly since purchase and you're right of course! Stupid question then, but where is the extra 32KB coming from??

Both the Slogger and the 6502 are soldered but I've ordered some dip sockets to remove it from the equation while troubleshooting. ULA is blob type so I'm gonna check for dry joints, but that's it I guess.

For the other Iss 2 Electron, I will do as you suggested and clean the ULA, checking the pins.

[paulb]

I've just reopened the Iss 6 as I hadn't really checked properly since purchase and you're right of course! Stupid question then, but where is the extra 32KB coming from??

It is static RAM, not dynamic RAM. Since RAM got quite a bit cheaper over the life of the Electron, as you might imagine, and since static RAM is easier to deal with, there are good reasons to use it in such expansions.

Both the Slogger and the 6502 are soldered but I've ordered some dip sockets to remove it from the equation while troubleshooting. ULA is blob type so I'm gonna check for dry joints, but that's it I guess.

For the other Iss 2 Electron, I will do as you suggested and clean the ULA, checking the pins.

I guess you must have seen the "Electron Start-Up Fault Gallery", which is an experiment attempting to catalogue various fault conditions in order to infer probable causes. The blob-type ULA is on a board and, as far as I recall, isn't generally a problem, although Adrian Black's Electron repair involved a machine where someone had desoldered that board and just left it like that.

[slikvik55]

Thanks for the explanation Paul; makes sense.

Yep, saw that thread and the fault with my rev. 2 - the black and white horizontal stripes - looked to be DRAM in the end. I'll still clean the ULA, because I can!

The slogger Electron (rev 6) is a bit more odd. Sometimes it boots but the text is corrupted, in all three modes: standard, 64k, and turbo. You can still make out the Electron 64k though which makes me think the Slogger is fine. Given this one is the soldered blob chip AND that in some cases I also get the black & white stripes, I'm going to assume it's also DRAM.

By the way, I love Adrian's channel and watched that one when it came out. Wild! Haha.

My rev2 fault:


My Rev 6 fault (when it's not also doing the image above:


Also, you should see the absolute bodge job on the keyboard of one of them, but I'll do another post for that haha.

[mogwaay]

DRAM manufacturers specially designed the 7 bit 128 cycle, 2ms refresh types to maintain compatibility with existing systems that were designed for 4116 DRAM chips. For example, Z80 systems and other MPU systems that had support circuitry with only 7 bit refresh counters.

These DRAM have 7 rows for refresh purposes. The refresh address must be on the A0 to A6 address input pins. Generally the value on A7 is ignored during refresh, so can be logic low or high.

Internally they appear to be comprised of four groups of 64 rows X 256 columns, hence 64K. See the datasheet for the Mitsubishi M5K4164ANP. Or eight groups of 32 rows X 256 columns, see the datasheet for the Motorola MCM6665A.

As the technology of DRAM improved and was further developed, the refresh period was increased to 4ms (256 cycle types). But also other refresh methods became available such as hidden refresh, CAS before RAS, and on chip refresh counter circuitry (meaning there was no longer a need for the system to provide a refresh controller).

Mark

Thanks, great explanation

[baz4096]

I don't have PM access yet as I haven't posted enough

I've enabled your PMs